US5218244A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic level converter circuit
Assignee: NEC Corp
•
Filing: 1992-02-26
•
Granted: 1993-06-08
•
Expires: 2012-02-26
Abstract
Abstract A logic level converter circuit for converting an ECL input signal to other type logic signal such as a TTL output signal comprises a differential comparator of an ECL type and an inverter which is formed by an output insulated-gate field-effect transistor and an output bipolar transistor connected in series between a higher potential power supply terminal and a lower potential power supply terminal. An output node of the differential comparator is directly connected to a gate of the output field-effect transistor and also coupled through a coupling capacitor to a base of the output bipolar transistor. An output of the differential comparator may be supplied to both the output transistors through an emitter follower circuit having a high driving capability. A bias voltage generating circuit may be provided for causing a DC bias current to flow in the output bipolar transistor. A change in the differential comparator output is immediately transmitted not only to the output field-effect transistor but also to the output bipolar transistor, so that it is possible to reduce the propagation delay time and to increase the operation speed of the circuit.
Inventors
- 👤 Jyoji Nokubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
154 words
A logic level converter circuit for converting an ECL level signal to other logic type level signal, said circuit comprising: a first and a second power supply terminal; a differential comparator including a differential pair of first and second bipolar transistors whose emitters are connected together, for outputting an output at an output node; and a level conversion means for converting the output of said differential comparator from said ECL level signal to said other logic type level signal. said level conversion means including an inverter and a capacitor, said inverter having an insulated-gate field-effect transistor whose gate is connected to said output node of said differential comparator and a third bipolar transistor connected in series with said insulated-gate field-effect transistor, said inverter being connected between said first and second power supply terminals, and said capacitor being connected between said output node of said differential comparator and a gate of said third bipolar transistor.
Claim 2
Dependent Claim
154 words
A logic level converter circuit for converting an ECL level signal to other logic type level signal, said circuit comprising: a first and a second power supply terminal; a differential comparator including a differential pair of first and second bipolar transistors whose emitters are connected together, for outputting an output at an output node; and a level conversion means for converting the output of said differential comparator from said ECL level signal to said other logic type level signal. said level conversion means including an inverter and a capacitor, said inverter having an insulated-gate field-effect transistor whose gate is connected to said output node of said differential comparator and a third bipolar transistor connected in series with said insulated-gate field-effect transistor, said inverter being connected between said first and second power supply terminals, and said capacitor being connected between said output node of said differential comparator and a gate of said third bipolar transistor.
Claim 3
Dependent Claim
49 words
A logic level converter circuit according to claim 1, in which said first and second power supply terminals are of a higher voltage and a lower voltage, respectively, said insulated-gate field-effect transistor is a P-channel MOS field-effect transistor and said first through third bipolar transistors are NPN-type bipolar transistors.
Claim 4
Dependent Claim
32 words
A logic level converter circuit according to claim 1, further comprising a bias voltage generating circuit connected to the base of said third bipolar transistor for supplying a predetermined bias voltage thereto.
Claim 5
Dependent Claim
55 words
A logic level converter circuit according to claim 3, in which said bias voltage generating circuit includes a load resistor and a fourth bipolar transistor having a collector connected to said first power supply terminal, a gate receiving a reference voltage, and an emitter connected to said second power supply terminal through said load resistor.
Claim 6
Dependent Claim
55 words
A logic level converter circuit according to claim 1, further comprising an emitter follower circuit whose input terminal is connected to the output node of said differential comparator and whose output terminal is connected to the gate of said insulated-gate field-effect transistor and coupled to the base of said third bipolar transistor through said capacitor.
Claim 7
Dependent Claim
54 words
A logic level converter circuit according to claim 5, in which said emitter follower circuit includes a bipolar transistor having a collector connected to said first power supply terminal, a gate connected to the output node of said differential comparator, and an emitter connected to said second power supply terminal through a constant-current source.
Claim 8
Dependent Claim
45 words
A logic level converter circuit according to claim 1, further comprising an emitter follower circuit whose input terminal is connected through said capacitor to the output node of said differential comparator and whose output terminal is connected to the gate of said third bipolar transistor.
Claim 9
Dependent Claim
86 words
A level converter circuit according to claim 7, in which said emitter follower circuit is formed by a double-emitter bipolar transistor having a collector connected to said first power supply terminal, a gate connected through said capacitor to the output node of said differential comparator, a first emitter connected to the base of said third bipolar transistor and to the second power supply terminal through a load resistor, and a second emitter connected to a collector of said third bipolar transistor through a resistor for clamping.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |