US5124581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Emitter-coupled logic output circuit
Assignee: NEC Corp
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Filing: 1991-09-23
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Granted: 1992-06-23
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Expires: 2011-09-23
Abstract
Abstract An ECL output circuit comprises a current-switching type logic circuit formed by differentially connected first and second bipolar transistors whose common emitters are connected to a lower potential power supply, and an emitter follower circuit formed by a third bipolar transistor whose collector is connected to a higher potential power supply and whose base is connected to a collector of one of the first and second bipolar transistors. The ECL output circuit further comprises a first N-type MOS transistor having a source connected to the lower potential power supply, and a gate and a drain commonly connected to the higher potential power supply through a resistor and to a collector of the other one of the first and second bipolar transistors through a capacitor, and a second N-type MOS transistor having a gate connected to the gate of the first MOS transistor, a source connected to the lower potential power supply, and a drain connected to the emitter of the third bipolar transistor. The circuit enables the discharging current of an output load to be increased only in the falling period of the output thereby realizing the high-speed operation, and where no logical change occurs, a very small constant-current flows in the circuit resulting in low power consumption.
Inventors
- 👤 Yoshitaka Umeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
222 words
An ECL output circuit having an input terminal, a reference potential terminal, an output terminal, a constant-current source, a higher potential supply terminal, a lower potential supply terminal, a resistor, and a capacitor, said output circuit comprising: a first bipolar transistor having a base connected to said input terminal and an emitter connected to said lower potential supply terminal through said constant-current source; a second bipolar transistor having a base connected to said reference potential terminal and an emitter connected to said lower potential supply terminal through said constant-current source; a third bipolar transistor having a collector connected to said higher potential supply terminal, an emitter connected to said output terminal, and a base connected to a collector of one of said first and second bipolar transistors; a first one-conductivity type MOS transitor having a source connected to said lower potential supply terminal, and a gate and a drain which are connected commonly to said higher potential supply terminal through said resistor and to a collector of the other one of said first and second bipolar transistors through said capacitor; and a second one-conductivity type MOS transistor having a gate connected to the gate of said first one-conductivity type MOS transistor, a source connected to said lower potential supply terminal, and a drain connected to the emitter of said third bipolar transistor.
Claim 2
Dependent Claim
222 words
An ECL output circuit having an input terminal, a reference potential terminal, an output terminal, a constant-current source, a higher potential supply terminal, a lower potential supply terminal, a resistor, and a capacitor, said output circuit comprising: a first bipolar transistor having a base connected to said input terminal and an emitter connected to said lower potential supply terminal through said constant-current source; a second bipolar transistor having a base connected to said reference potential terminal and an emitter connected to said lower potential supply terminal through said constant-current source; a third bipolar transistor having a collector connected to said higher potential supply terminal, an emitter connected to said output terminal, and a base connected to a collector of one of said first and second bipolar transistors; a first one-conductivity type MOS transitor having a source connected to said lower potential supply terminal, and a gate and a drain which are connected commonly to said higher potential supply terminal through said resistor and to a collector of the other one of said first and second bipolar transistors through said capacitor; and a second one-conductivity type MOS transistor having a gate connected to the gate of said first one-conductivity type MOS transistor, a source connected to said lower potential supply terminal, and a drain connected to the emitter of said third bipolar transistor.
Claim 3
Dependent Claim
56 words
An ECL output circuit according to claim 1, in which a plurality of third one-conductivity type MOS transistors each having the same configuration as that of said second one-conductivity type MOS transistor are connected in parallel to said second one-conductivity type MOS transistor in accordance with an increase of a load capacitance at said output terminal.
Claim 4
Dependent Claim
33 words
An ECL output circuit according to claim 1, in which said first to third bipolar transistors are of an NPN-type, and said first and second one-conductivity type MOS transistors are of an N-type.
Claim 5
Dependent Claim
20 words
An ECL output circuit according to claim 2, in which said third one-conductivity type MOS transitors are of an N-type.
Claim 6
Dependent Claim
242 words
An ECL output circuit having an input terminal, a reference potential terminal, an output terminal, a constant-current source, a higher potential supply terminal, a first lower supply terminal, a second lower potential supply terminal having a potential higher than that of said first lower potential supply terminal, a resistor and a capacitor, said output circuit comprising: a first bipolar transistor having a base connected to said input terminal and an emitter connected to said first lower potential supply terminal through said constant-current source; a second bipolar transistor having a base connected to said reference potential terminal and an emitter connected said first lower potential supply terminal through said constant-current source; a third bipolar transistor having a collector connected to said higher potential supply terminal, an emitter connected to said output terminal, and a base connected to a collector of one of said first and second bipolar transistors; a first one-conductivity type MOS transistor having a source connected to said second lower potential supply terminal, and a gate and a drain which are connected commonly to said higher potential supply terminal through said resistor and to a collector of one of said first and second bipolar transistors through said capacitor; and a second one-conductivity type MOS transistor having a gate connected to the gate of said first one-conductivity type MOS transistor, a source connected to said second lower potential supply terminal, and a drain connected to the emitter of said third bipolar transistor.
Claim 7
Dependent Claim
242 words
An ECL output circuit having an input terminal, a reference potential terminal, an output terminal, a constant-current source, a higher potential supply terminal, a first lower supply terminal, a second lower potential supply terminal having a potential higher than that of said first lower potential supply terminal, a resistor and a capacitor, said output circuit comprising: a first bipolar transistor having a base connected to said input terminal and an emitter connected to said first lower potential supply terminal through said constant-current source; a second bipolar transistor having a base connected to said reference potential terminal and an emitter connected said first lower potential supply terminal through said constant-current source; a third bipolar transistor having a collector connected to said higher potential supply terminal, an emitter connected to said output terminal, and a base connected to a collector of one of said first and second bipolar transistors; a first one-conductivity type MOS transistor having a source connected to said second lower potential supply terminal, and a gate and a drain which are connected commonly to said higher potential supply terminal through said resistor and to a collector of one of said first and second bipolar transistors through said capacitor; and a second one-conductivity type MOS transistor having a gate connected to the gate of said first one-conductivity type MOS transistor, a source connected to said second lower potential supply terminal, and a drain connected to the emitter of said third bipolar transistor.
Claim 8
Dependent Claim
33 words
An ECL output circuit according to claim 5, in which said first to third bipolar transistors are of an NPN-type, and said first and second one-conductivity type MOS transistors are of an N-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |