US5003199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Emitter coupled logic circuit having an active pull-down output stage
Assignee: International Business Machines Corp
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Filing: 1990-02-26
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Granted: 1991-03-26
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Expires: 2010-02-26
Abstract
Abstract An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of the device impedance during switching of the device from pull-up to pull-down operation, resulting in an improved pull-down speed.
Inventors
- 👤 Ching-Te K. Chuang
- 👤 Hyun J. Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K17/00; H03K17/51; H03K17/56; H03K17/567
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
An emitter coupled logic circuit comprising: a bipolar transistor pull-up circuit having a base connected to a ECL logic stage circuit, and having an emitter-collector circuit connected to an output terminal and a power supply first terminal, providing a first voltage to said terminal in response to a first logic state applied from said logic stage; a junction field effect transistor pull-down circuit having a gate connected to said ECL logic stage circuit a source-drain circuit connected to said output terminal and a second terminal of said power supply, and a back gate connected to enable conduction of said source-drain circuit, whereby during switching of said logic stage circuit from a first logic state to a second logic state, said output terminal is connected through an impedance which initially decreases, and then increases as a load connected to said output terminal reaches a potential associated with said second logic state.
Claim 2
Dependent Claim
150 words
An emitter coupled logic circuit comprising: a bipolar transistor pull-up circuit having a base connected to a ECL logic stage circuit, and having an emitter-collector circuit connected to an output terminal and a power supply first terminal, providing a first voltage to said terminal in response to a first logic state applied from said logic stage; a junction field effect transistor pull-down circuit having a gate connected to said ECL logic stage circuit a source-drain circuit connected to said output terminal and a second terminal of said power supply, and a back gate connected to enable conduction of said source-drain circuit, whereby during switching of said logic stage circuit from a first logic state to a second logic state, said output terminal is connected through an impedance which initially decreases, and then increases as a load connected to said output terminal reaches a potential associated with said second logic state.
Claim 3
Dependent Claim
18 words
The emitter coupled logic circuit of claim 1 wherein said back gate is connected to said gate connection.
Claim 4
Dependent Claim
17 words
The emitter coupled logic circuit of claim 1 wherein said back gate is connected to said terminal.
Claim 5
Dependent Claim
110 words
An emitter coupled logic circuit for supplying a load with first and second logic levels comprising: a pull-up circuit connected to supply a first voltage level to said load in response to a first signal from an ECL logic stage; a pull-down circuit connected to supply a second voltage level to said load, comprising a junction field effect transistor connecting said load to a second voltage level in response to a second signal from said ECL logic stage, said junction field effect transistor having a back gate connected to a potential which increases current flow from said load through said junction field effect transistor in response to said second signal.
Claim 6
Dependent Claim
110 words
An emitter coupled logic circuit for supplying a load with first and second logic levels comprising: a pull-up circuit connected to supply a first voltage level to said load in response to a first signal from an ECL logic stage; a pull-down circuit connected to supply a second voltage level to said load, comprising a junction field effect transistor connecting said load to a second voltage level in response to a second signal from said ECL logic stage, said junction field effect transistor having a back gate connected to a potential which increases current flow from said load through said junction field effect transistor in response to said second signal.
Claim 7
Dependent Claim
52 words
The emitter coupled logic circuit of claim 4 wherein said back gate is connected to said ECL logic stage, and receives said second signal which initially lowers said junction field effect transistor impedance during a transition period when said ECL logic circuit switches from providing said first signal to said second signal.
Claim 8
Dependent Claim
50 words
The emitter coupled logic circuit of claim 5 further comprising a bipolar transistor having a base emitter circuit connected in series with said junction field effect transistor drain, and a collector connected to said load, whereby said bipolar transistor decreases the impedance between the load and said second voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |