ECL circuit with low voltage/fast pull-down

Claim 2

A logic circuit which comprises: an input stage; an output stage coupled to the input stage; a low-voltage inverter stage coupled to the input stage; an active pull-down stage coupled too the low-voltage inverter stage and to the output stage; means for pre-biasing the active pull-down stage such that the active pull-down stage is pre-biased to be slightly conductive, wherein the output stage comprises a first transistor having a collector, a base, and an emitter, the collector being coupled to a positive voltage supply terminal, the base being coupled to the input stage, and the emitter being coupled to the active pull-down stage and to an output terminal; and wherein the active pull-down stage comprises: a second transistor having a collector, a base, and an emitter, the collector being coupled to the output stage and to the output terminal, and the base being coupled to the means for pre-biasing; and a first resistor having a first end and a second end, the first end being coupled to the emitter of the second transistor, and the second end being coupled to a negative voltage supply terminal.

Claim 3

The logic circuit of claim 1 wherein an output of the inverter stage is coupled to the active pull-down stage by means of: an emitter follower having a collector, a base, and an emitter, the collector being coupled to the positive voltage supply terminal, and the base being coupled to the output of the inverter stage.

Claim 4

The logic circuit of claim 2 wherein the inverter stage, the active pull-down stage, and the means for pre-biasing operate at a supply voltage less than one half of a supply voltage poor the input stage.

Claim 5

The logic circuit of claim 2 wherein the inverter stage comprises: a second resistor having a first end and a second end, the first end being coupled to the positive voltage supply terminal; a third resistor having a first end and a second end, the first end being coupled t the second end of the second resistor, and the second end being coupled to the negative voltage supply terminal; a fourth resistor having a first end and a second end, the first end being coupled to the positive voltage supply terminal; a third transistor having a collector, a base, and an emitter, the collector being coupled to the second end of the fourth resistor, and wherein the collector serves as the output of the inverter, and the base being coupled to the input stage; a fourth transistor having a collector, a base, and an emitter, the collector being coupled to the positive voltage supply terminal, the base being coupled to the second end of the second resistor and to the first end of the third resistor, and the emitter being coupled to the emitter of the third transistor; and a fifth resistor having a first end and a second end, the first end being coupled to the emitters of the third and fourth transistors, and the second end being coupled to the negative voltage supply terminal; and a sixth resistor having a first end and a second end, the first end being coupled to the emitter of the emitter follower, and the second end being coupled to the negative voltage supply terminal.

Claim 6

The logic circuit of claim 4 wherein the means for pre-biasing the active pull-down device comprises: a fifth transistor having a collector, a base, and an emitter, the collector being coupled to the base; a sixth transistor having a collector, a base, and an emitter, the collector being coupled to the positive voltage supply terminal, the base being coupled to the collector and the base of the fifth transistor, and the emitter being coupled to the active pull-down stage; a seventh transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, the collector being coupled to the base, and further being coupled to the emitter of the fifth transistor; an eighth transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, the collector being coupled to the emitter of the sixth transistor and to the active pull-down stage, and the base being coupled to the base and collector of the seventh transistor and to the emitter of the fifth transistor; and a current source coupled between the positive voltage supply terminal and the collector and base of the fifth transistor and the base of the sixth transistor such that ten to fifty microamps of current are sourced.

Claim 7

The logic circuit of claim 4 wherein the means for pre-biasing the active pull-down device comprises: a fifth transistor having a collector, a base, and an emitter, the collector being coupled to the base; a sixth transistor having a collector, a base, and an emitter, the collector being coupled to the positive voltage supply terminal, the base being coupled to the collector and the base of the fifth transistor, and the emitter being coupled to the active pull-down stage; a seventh transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, the collector being coupled to the base, and further being coupled to the emitter of the fifth transistor; an eighth transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, the collector being coupled to the emitter of the sixth transistor and to the active pull-down stage, and the base being coupled to the base and collector of the seventh transistor and to the emitter of the fifth transistor; and a ninth transistor having a source, a gate, and a drain, the source being coupled to the positive voltage supply terminal, the gate being coupled to the negative voltage supply terminal, and the drain being coupled to the collector and base of the fifth transistor and the base of the sixth transistor such that ten to fifty microamps of current are sourced.

Claim 8

The logic circuit of claim 4 wherein the means for pre-biasing the active pull-down device comprises: a fifth transistor having a collector, a base, and an emitter, the collector being coupled to the base, and the emitter being coupled to the negative voltage supply; a sixth resistor having two ends, the first end being coupled to the collector and base of the fifth transistor, and the second end being coupled to the active pull-down stage; and a current source coupled between the emitter of the emitter follower, and the collector and base of the fifth transistor such that ten to fifty microamps of current are sourced.

Claim 9

The logic circuit of claim 4 wherein the means for pre-biasing the active pull-down device comprises: a fifth transistor having a collector, a base, and an emitter, the collector being coupled to the base, and the emitter being coupled to the negative voltage supply; a sixth resistor having two ends, the first end being coupled to the collector and base of the fifth transistor, and the second end being coupled to the active pull-down stage; and a sixth transistor having a source, a gate, and a drain, the source being coupled to the collector and base of the fifth transistor, the gate being coupled to the positive voltage supply terminal, and the drain being coupled to the emitter of the emitter follower, such that ten to fifty microamps of current are sourced.

Claim 10

The logic circuit of claim 2 wherein the inverter stage comprises: a second resistor having a first end and a second end, the first end being coupled to the positive voltage supply terminal; a third resistor having a first end and a second end, the first end being coupled to the second end of the second resistor; a fourth resistor having a first end and a second end, the first end being coupled to the second end f the third resistor, and the second end being coupled to the negative voltage supply terminal; a fifth resistor having a first end and a second end, the first end being coupled to the positive voltage supply terminal; a third transistor having a collector, a base, and an emitter, the collector being coupled to the second end of the fifth resistor, wherein the collector serves as the output of the inverter, and the base being coupled to the input stage; a fourth transistor having a collector, a base and an emitter, the collector being coupled to the positive voltage supply terminal, the base being coupled to the second end of the second resistor and to the first end of the third resistor, and the emitter being coupled to the emitter of the third transistor; a sixth resistor having a first end and a second end, the first end being coupled to the emitters of the third and fourth transistors, and the second end being coupled to the negative voltage supply terminal; and a seventh resistor having a first end and a second end, the first end being coupled too the emitter of the emitter follower, and the second end being coupled to the negative voltage supply terminal.

Claim 11

The logic circuit of claim 9 wherein the active pull-down stage couples to the second end of the third resistor and to the first end of the fourth resistor.

Claim 12

An emitter coupled logic circuit which comprises: a first negative power supply terminal providing a first power supply voltage; a second negative power supply terminal providing a second power supply voltage, the second power supply voltage being less than half of the first power supply voltage; an input stage coupled to the first negative power supply terminal; at least one output stage coupled to the input stage; at least one active pull-down stage coupled to the at least one output stage, and further coupled to the second negative power supply terminal; and means for pre-biasing the active pull-down stage such that the active pull-down stage is pre-biased to be slightly conductive.

Claim 13

An emitter coupled logic circuit which comprises: a first negative power supply terminal providing a first power supply voltage; a second negative power supply terminal providing a second power supply voltage, the second power supply voltage being less than half of the first power supply voltage; an input stage coupled to the first negative power supply terminal; at least one output stage coupled to the input stage; at least one active pull-down stage coupled to the at least one output stage, and further coupled to the second negative power supply terminal; and means for pre-biasing the active pull-down stage such that the active pull-down stage is pre-biased to be slightly conductive.

Claim 14

An emitter-coupled logic circuit which comprises: ann input stage; an output terminal; means for active pull-up coupled to the input stage and to the output terminal; means for active pull-down coupled to the output terminal; means for inverting an output of the input stage coupled to the input stage and to the means for active pull-down; means for pre-biasing the means for active pull-down to a slightly conductive state, coupled to the means for active pull-down; and wherein the means for inverting an output of the input stage comprises: a voltage divider; and a differential amplifier with two inputs and an output, the first input being coupled to the output of the input stage, the second input being coupled to the voltage divider, and the output being coupled to the means for active pull-down.

Claim 15

An emitter-coupled logic circuit which comprises: ann input stage; an output terminal; means for active pull-up coupled to the input stage and to the output terminal; means for active pull-down coupled to the output terminal; means for inverting an output of the input stage coupled to the input stage and to the means for active pull-down; means for pre-biasing the means for active pull-down to a slightly conductive state, coupled to the means for active pull-down; and wherein the means for inverting an output of the input stage comprises: a voltage divider; and a differential amplifier with two inputs and an output, the first input being coupled to the output of the input stage, the second input being coupled to the voltage divider, and the output being coupled to the means for active pull-down.

Claim 16

The logic circuit of claim 12 wherein an output of the means for inverting an output of the input stage couples to the means for active pull-down by means of: a transistor having a collector, a base, and an emitter, the collector being coupled to a positive voltage supply terminal, and the base being coupled to the output of the means for inverting an output of the input stage; and a capacitor having two ends, the first end being coupled to the emitter of the transistor, and the second end being coupled to the means for active pull-down.

Claim 17

The logic circuit of claim 12 wherein the means for pre-biasing the active pull-down comprises: a first transistor having a collector, a base, and an emitter, the collector being coupled to the base; a second transistor having a collector, a base, and an emitter, the collector being coupled to the positive voltage supply terminal, the base being coupled to the collector and the base of the first transistor, and the emitter being coupled to the means for active pull-down; a third transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, and the collector being coupled to the base, and further being coupled to the emitter of the first transistor; a fourth transistor having a collector, a base, and an emitter, the emitter being coupled to the negative voltage supply terminal, the collector being coupled to the emitter of the second transistor and to the means for active pull-down, and the base being coupled to the base and collector of the third transistor and to the emitter of the first transistor; and a fifth transistor having a source, a gate, and a drain, the source being coupled to the positive voltage supply terminal, the gate being coupled to the negative voltage supply terminal, and the drain being coupled to the collector and base of the first transistor and the base of the second transistor such that ten to fifty microamps of current are sourced.