Patent US185489A successfully refreshed from Google Patents.
US5073728A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active load for ECL type outputs
Assignee: Texas Instruments Inc
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Filing: 1990-11-05
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Granted: 1991-12-17
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Expires: 2010-11-05
Abstract
Abstract An active pull down circuit for a logic circuit, having a true and a complement output, a pull down transistor coupled to one of the true and complement outputs, a bias element for biasing the pull down transistor on, and a charge coupling element coupled between the other of the true and complement outputs and a base of the pull down transistor for coupling charge from the other output to the pull down transistor to turn on the latter harder when the other output goes low.
Inventors
- 👤 Kevin M. Ovens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
169 words
An active load circuit for a logic output circuit, which has a true output, a complementary output, and external reference line and a reference supply voltage line, said active load circuit comprising: a first transistor having a collector connected to said true output, an emitter connected to said reference supply voltage line, and a base; a second transistor having a collector connected to said complementary output, an emitter connected to said reference supply voltage line, and a base; a bias circuit having an output coupled to said bases of said first and second transistors and said external reference line and having an input connected to said reference supply voltage line, said bias circuit supplying bias current to said first and second transistors; a first charge coupling element connected between and for coupling charge between said base of said first transistor and said complementary output lead; and a second charge coupling element connected between and for coupling charge between said base of said second transistor and said true output lead.
Claim 2
Dependent Claim
169 words
An active load circuit for a logic output circuit, which has a true output, a complementary output, and external reference line and a reference supply voltage line, said active load circuit comprising: a first transistor having a collector connected to said true output, an emitter connected to said reference supply voltage line, and a base; a second transistor having a collector connected to said complementary output, an emitter connected to said reference supply voltage line, and a base; a bias circuit having an output coupled to said bases of said first and second transistors and said external reference line and having an input connected to said reference supply voltage line, said bias circuit supplying bias current to said first and second transistors; a first charge coupling element connected between and for coupling charge between said base of said first transistor and said complementary output lead; and a second charge coupling element connected between and for coupling charge between said base of said second transistor and said true output lead.
Claim 3
Dependent Claim
15 words
The active load circuit of claim 1 in which said charge coupling elements are capacitors.
Claim 4
Dependent Claim
36 words
The active load circuit of claim 1 in which said bias circuit includes a current source supplying current and connected between said first and second leads and a diode connected transistor connected in said second lead.
Claim 5
Dependent Claim
42 words
The active load circuit of claim 1 in which said bias circuit includes a first resistor connecting said base of said first transistor to said first lead and a second resistor connecting said base of said second transistor to said first lead.
Claim 6
Dependent Claim
35 words
The active load circuit of claim 4 in which said charge coupling elements are capacitors and said resistors and capacitors being selected to furnish a time constant in the range of 0.5 to 2.0 nanoseconds.
Claim 7
Dependent Claim
50 words
The active load circuit of claim 1 in which said logic output circuit passes a quiescent current and said active load circuit passes a quiescent current through said first and second transistors and said bias circuit in the range of 1/10 to 1/100 of the logic output circuit quiescent current.
Claim 8
Dependent Claim
75 words
The active load circuit of claim 1 in which said logic output circuit includes a pair of differential transistors each having emitters connected together and coupled to said reference supply voltage line by a current source, said pair of differential transistors each having collectors, said logic output circuit further including a true and a complementary output transistor respectively connected between a collector of said pair of differential transistors and said true and complementary output leads.
Claim 9
Dependent Claim
20 words
The active load circuit of claim 1 in which said reference supply voltage line is a negative supply voltage line.
Claim 10
Dependent Claim
41 words
The active load circuit of claim 1 in which said bias circuit includes a diode connected transistor selected to supply bias current to said first and second transistors that biases said first and second transistors on but close to cut off.
Claim 11
Dependent Claim
145 words
An active load circuit for a logic output circuit, which has at least a true output lead, a complementary output lead, an external reference line and a reference supply voltage line, said active load circuit comprising: at least one load transistor having a collector connected to one of said output leads, an emitter connected to said reference supply line, and a base; a bias circuit having an output connected to said at least one load transistor and to said external reference line, and an input connected to said reference supply voltage line, said bias circuit supplying bias current to said at least one load transistor sufficient to bias on said at least one load transistor but with a bias current close to cut off; and a capacitor connected between the base of said at least one load transistor and the other of said output leads.
Claim 12
Dependent Claim
145 words
An active load circuit for a logic output circuit, which has at least a true output lead, a complementary output lead, an external reference line and a reference supply voltage line, said active load circuit comprising: at least one load transistor having a collector connected to one of said output leads, an emitter connected to said reference supply line, and a base; a bias circuit having an output connected to said at least one load transistor and to said external reference line, and an input connected to said reference supply voltage line, said bias circuit supplying bias current to said at least one load transistor sufficient to bias on said at least one load transistor but with a bias current close to cut off; and a capacitor connected between the base of said at least one load transistor and the other of said output leads.
Claim 13
Dependent Claim
25 words
The active load circuit of claim 10 in which there are two load transistors, each having an emitter connected to said reference supply voltage line.
Claim 14
Dependent Claim
52 words
The active load circuit of claim 10 in which said bias circuit includes a current source supplying current, a diode connected transistor connected between said current source and said reference supply voltage line, and an isolating resistor connected between said current source and said base of said at least one load transistor.
Claim 15
Dependent Claim
20 words
The active load circuit of claim 10 in which said reference supply voltage line is a negative supply voltage line.
Claim 16
Dependent Claim
75 words
The active load circuit of claim 10 in which said logic output circuit includes a pair of differential transistors each having emitters connected together and coupled to said reference supply voltage line by a current source, said pair of differential transistors each having collectors, said logic output circuit further including a true and a complementary output transistor respectively connected between a collector of said pair of differential transistors and said true and complementary output leads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |