US4626709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic push-pull for ECL
Assignee: Advanced Micro Devices Inc
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Filing: 1984-09-28
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Granted: 1986-12-02
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Expires: 2004-09-28
Abstract
Abstract An improved ECL gate having faster output transition times without requiring additional current is provided. Two switching transistors have their emitter terminals connected to a first current source. A reference switching transistor has its base connected to a reference voltage and an input switching transistor has its base connected to an input terminal. An emitter follower transistor is coupled to each switching transistor. A second current source is connected to each of the emitter follower transistors by coupling circuitry which shunts current from one emitter follower to the other thereby increasing the transition speed of the outputs. In the preferred embodiment, the emitters of the current source transistors for the two outputs are coupled through a common resistance to ground. The collector of the inverting emitter-coupled transistor is coupled via a capacitor to the base of the current source transistor for the non-inverting output. The collector of the non-inverting emitter-coupled transistor is coupled via a second capacitor to the base of the current source transistor for the inverting output. The base of each such current source transistor is coupled to a current source voltage via a resistance or a diode. The capacitance coupling essentially causes only one of such current source transistors to be turned on at any one time during switching. This forces all the current through one or the other of the current source transistors, thus allowing the output which requires such current to change states faster.
Inventors
- 👤 Nikhil C. Mazumder
- 👤 II Frederick N. Lancia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
318 words
An emitter coupled logic (ECL) circuit comprising: at least two switching transistors formed of a reference switching transistor and an input switching transistor and having their emitter terminals coupled to a first current source, said reference switching transistor having a base terminal coupled to a reference voltage terminal, said input switching transistor having a base terminal coupled to an input terminal; a pair of emitter follower transistors, a first emitter follower transistor coupled to the reference switching transistor, a second emitter follower transistor coupled to the input switching transistor; a second current source connected to each transistor of the emitter follower pair; means connected to each switching transistor for exclusively coupling the second current source to one of the first and second emitter follower transistors dependent upon which switching transistor is conductive; said coupling means including a pair of coupling transistors having their emitter terminals connected to said second current source, a first coupling transistor having its collector terminal connected to an emitter terminal of the first emitter follower transistor and its base terminal coupled to a collector terminal of the input switching transistor, a second coupling transistor having its collector terminal connected to an emitter terminal of the second emitter follower transistor and its base terminal coupled to a collector terminal of the reference switching transistor; each base terminal of the coupling transistor pair being connected to the collector terminals of the switching transistors by capacitance means; said second current source being formed of a resistance means connected between the emitter terminals of the coupling transistors and a voltage supply terminal; and a diode being connected between each of the base terminals of the coupling transistors and a current source voltage terminal to prevent any current from flowing between the base terminals and the current source voltage terminal during switching; whereby the delay in switching speeds caused by load capacitance on the emitter follower transistors is reduced.
Claim 2
Dependent Claim
318 words
An emitter coupled logic (ECL) circuit comprising: at least two switching transistors formed of a reference switching transistor and an input switching transistor and having their emitter terminals coupled to a first current source, said reference switching transistor having a base terminal coupled to a reference voltage terminal, said input switching transistor having a base terminal coupled to an input terminal; a pair of emitter follower transistors, a first emitter follower transistor coupled to the reference switching transistor, a second emitter follower transistor coupled to the input switching transistor; a second current source connected to each transistor of the emitter follower pair; means connected to each switching transistor for exclusively coupling the second current source to one of the first and second emitter follower transistors dependent upon which switching transistor is conductive; said coupling means including a pair of coupling transistors having their emitter terminals connected to said second current source, a first coupling transistor having its collector terminal connected to an emitter terminal of the first emitter follower transistor and its base terminal coupled to a collector terminal of the input switching transistor, a second coupling transistor having its collector terminal connected to an emitter terminal of the second emitter follower transistor and its base terminal coupled to a collector terminal of the reference switching transistor; each base terminal of the coupling transistor pair being connected to the collector terminals of the switching transistors by capacitance means; said second current source being formed of a resistance means connected between the emitter terminals of the coupling transistors and a voltage supply terminal; and a diode being connected between each of the base terminals of the coupling transistors and a current source voltage terminal to prevent any current from flowing between the base terminals and the current source voltage terminal during switching; whereby the delay in switching speeds caused by load capacitance on the emitter follower transistors is reduced.
Claim 3
Dependent Claim
40 words
The ECL circuit of claim 1 wherein said diode means comprises a pair of diodes, said diodes having their cathode connected to the base terminals of said current source transistors and having their anode connected to the current source voltage.
Claim 4
Dependent Claim
20 words
The ECL circuit of claim 1 wherein the capacitance means comprises a transistor having its collector connected to its emitter.
Claim 5
Dependent Claim
21 words
The ECL circuit of claim 1 wherein each of the diodes comprise a transistor having its collector connected to its base.
Claim 6
Dependent Claim
55 words
The ECL circuit of claim 1 further comprising at least a third switching transistor having an emitter terminal connected to the first current source, a collector terminal connected to the collector terminal of the input switching transistor and a base terminal connected to a second input terminal, whereby a multiple input logic circuit is formed.
Claim 7
Dependent Claim
254 words
An emitter coupled logic (ECL) circuit comprising; at least two switching transistors formed of a reference switching transistor and an input switching transistor and having their emitter terminals coupled to a first current source, said reference switching transistor having a base terminal connected to a reference voltage terminal, said input switching transistor having a base terminal connected to an input terminal; a pair of emitter follower transistors, a first emitter follower transistor connected to the reference switching transistor, a second emitter follower transistor connected to the input switching transistor; a current source resistor coupled to a voltage supply terminal; a pair of current source transistors having their emitter terminals connected to said current source resistor, a first current source transistor having its collector terminal connected to an emitter terminal of the first emitter follower transistor, a second current source transistor having its collector terminal connected to an emitter terminal of the second emitter follower transistor; a pair of capacitors, a first capacitor coupling the base terminal of said first current source transistor to a collector terminal of the input switching transistor, a second capacitor coupling the base terminal of said second current source transistor to a collector terminal of the reference switching transistor; and diode means, coupling the base terminals of said current source transistors to a current source voltage, for preventing any current from flowing between the base terminals and the current source voltage during switching; whereby the delay in switching speeds caused by load capacitance on the emitter follower transistors is reduced.
Claim 8
Dependent Claim
254 words
An emitter coupled logic (ECL) circuit comprising; at least two switching transistors formed of a reference switching transistor and an input switching transistor and having their emitter terminals coupled to a first current source, said reference switching transistor having a base terminal connected to a reference voltage terminal, said input switching transistor having a base terminal connected to an input terminal; a pair of emitter follower transistors, a first emitter follower transistor connected to the reference switching transistor, a second emitter follower transistor connected to the input switching transistor; a current source resistor coupled to a voltage supply terminal; a pair of current source transistors having their emitter terminals connected to said current source resistor, a first current source transistor having its collector terminal connected to an emitter terminal of the first emitter follower transistor, a second current source transistor having its collector terminal connected to an emitter terminal of the second emitter follower transistor; a pair of capacitors, a first capacitor coupling the base terminal of said first current source transistor to a collector terminal of the input switching transistor, a second capacitor coupling the base terminal of said second current source transistor to a collector terminal of the reference switching transistor; and diode means, coupling the base terminals of said current source transistors to a current source voltage, for preventing any current from flowing between the base terminals and the current source voltage during switching; whereby the delay in switching speeds caused by load capacitance on the emitter follower transistors is reduced.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |