US5796673A
Expired / Lapsed
US
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Delay locked loop implementation in a synchronous dynamic random access memory
Assignee: Mosaid Technologies Inc
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Filing: 1994-10-06
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Granted: 1998-08-18
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Expires: 2014-10-06
Abstract
Abstract A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Inventors
- 👤 Richard C. Foss
- 👤 Peter B. Gillingham
- 👤 Graham Allan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:36
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/00; G11C7/10; G11C7/1051; G11C7/1072; G11C7/22; G11C7/222; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/0814
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
259 words
A clock applying circuit for a synchronous memory comprising: (a) a clock input for receiving a clock input signal, (b) means connected to the synchronous memory for receiving a driving clock signal, (c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal, (d) means for selecting said output from said one of the delay elements, (e) means for providing the driving clock signal from an output of one of the delay elements, (f) the selecting means being comprised of a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of the clock input signal following an enable time required at a particular enable terminal-of the synchronous memory, (g) means for providing the driving clock signal to said particular enable terminal, (h) delay model means having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, and (i) an input port of the delay model means for receiving the driving clock signal and for providing a delayed driving signal to the comparator.
Claim 2
Dependent Claim
259 words
A clock applying circuit for a synchronous memory comprising: (a) a clock input for receiving a clock input signal, (b) means connected to the synchronous memory for receiving a driving clock signal, (c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal, (d) means for selecting said output from said one of the delay elements, (e) means for providing the driving clock signal from an output of one of the delay elements, (f) the selecting means being comprised of a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of the clock input signal following an enable time required at a particular enable terminal-of the synchronous memory, (g) means for providing the driving clock signal to said particular enable terminal, (h) delay model means having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said particular enable terminal, and (i) an input port of the delay model means for receiving the driving clock signal and for providing a delayed driving signal to the comparator.
Claim 3
Dependent Claim
47 words
A clock applying circuit as defined in claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof and for outputting one of the output signals as the driving clock signal.
Claim 4
Dependent Claim
66 words
A clock applying circuit as defined in claim 1 in which the selecting means is comprised of a multiplexer for receiving output signals of plural ones of the delay elements at respective inputs thereof, means for receiving an input select control signal from the comparator resulting from said comparing for selecting one of said output signals for passing through the multiplexer as the driving clock signal.
Claim 5
Dependent Claim
235 words
A clock applying circuit comprising: (a) a synchronous dynamic random access memory (SDRAM) comprised of a memory array and an output buffer connected to the memory array, the memory array having a clock input signal terminal for receiving a driving clock signal, (b) a clock input for receiving a clock input signal, (c) a tapped delay line comprised of a series of delay elements and having an input, (d) means for applying the clock input signal to the clock input signal terminal and to the input of the tapped delay line, (e) means for receiving output signals of plural ones of the delay elements and for providing one of the output signals of the delay elements as the driving clock signal, (f) means for applying said driving clock signal to the enable terminal of the output buffer, (g) means for selecting said one of the output signals having a predetermined one of a rising and falling edge time which follows a corresponding rising or falling edge of the clock input signal by a clock skew delay time of the SDRAM between said clock input signal terminal of the memory array and the output buffer, (h) the receiving and providing means being comprised of a multiplexer for receiving said output signals at input terminals thereof and for receiving control signals from said selecting means for outputting one of said output signals as said driving clock signal.
Claim 6
Dependent Claim
235 words
A clock applying circuit comprising: (a) a synchronous dynamic random access memory (SDRAM) comprised of a memory array and an output buffer connected to the memory array, the memory array having a clock input signal terminal for receiving a driving clock signal, (b) a clock input for receiving a clock input signal, (c) a tapped delay line comprised of a series of delay elements and having an input, (d) means for applying the clock input signal to the clock input signal terminal and to the input of the tapped delay line, (e) means for receiving output signals of plural ones of the delay elements and for providing one of the output signals of the delay elements as the driving clock signal, (f) means for applying said driving clock signal to the enable terminal of the output buffer, (g) means for selecting said one of the output signals having a predetermined one of a rising and falling edge time which follows a corresponding rising or falling edge of the clock input signal by a clock skew delay time of the SDRAM between said clock input signal terminal of the memory array and the output buffer, (h) the receiving and providing means being comprised of a multiplexer for receiving said output signals at input terminals thereof and for receiving control signals from said selecting means for outputting one of said output signals as said driving clock signal.
Claim 7
Dependent Claim
96 words
A clock applying circuit as defined in claim 4 including a delay model means having a signal time delay simulating clock skew delay between a clock input terminal of the synchronous memory for receiving the clock input signal and said enable terminal, an input port of the delay model means for receiving the driving clock signal and for providing a delayed driving signal, the selecting means comprising comparing means for receiving the clock input signal and the delayed driving clock signal and for providing said control signals based on a zero or positive time differential thereof.
Claim 8
Dependent Claim
16 words
A clock applying circuit as defined in claim 5, integrated into a single integrated circuit chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |