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US5287319A Expired / Lapsed US ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory device

Assignee: Sharp Corp
•
Filing: 1991-05-23
•
Granted: 1994-02-15
•
Expires: 2011-05-23
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Abstract

Abstract In the normal selfrefresh mode, the timer output selection circuit selects the timer output of a longer cycle from the timer outputs generated by the internal timer circuit, and the selected timer output supplied as an operation activation signal for the selfrefresh operation. Using this long timer output, the selfrefresh operation of DRAM cells in the memory device is performed with a low operating current which allows the memory device to be backed up by a battery. When the selfrefresh mode is set before the store operation, the timer output of a short cycle is selected from the timer outputs generated by the internal timer circuit, and the short timer output is supplied as an operation activation signal for the selfrefresh operation. Using this short timer output, the selfrefresh operation of the volatile memory means is performed. Therefore, a drop in the potential of the volatile memory portions caused by a leakage current can be quickly compensated, thus ensuring that data can be correctly stored in the volatile memory means. In the selfrecall operation mode, the timer output of an medium cycle is selected from the timer outputs generated by the internal timer circuit, and the medium timer output is supplied as an operation activation signal for the selfcall operation. Since the selfrecall operation is performed using the medium timer output, the selfrecall operation is performed at a faster speed than the normal selfrefresh operation.

Inventors

  • 👤 Katsumi Fukumoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 13:25
CPC Classifications
G; G11; G11C; G11C14/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 85 words
A semiconductor memory device comprising: a plurality of memory cells each of which comprises volatile memory means and nonvolatile memory means; and a plurality of word lines, said semiconductor memory device further comprising: an internal timer circuit for generating at least two timer outputs, the cycles of said timer outputs being different to each other; and a timer output selection circuit for receiving said timer outputs, and for selectively supplying one of said timer outputs to said word lines as a word line activation signal.
Claim 2
Dependent Claim 85 words
A semiconductor memory device comprising: a plurality of memory cells each of which comprises volatile memory means and nonvolatile memory means; and a plurality of word lines, said semiconductor memory device further comprising: an internal timer circuit for generating at least two timer outputs, the cycles of said timer outputs being different to each other; and a timer output selection circuit for receiving said timer outputs, and for selectively supplying one of said timer outputs to said word lines as a word line activation signal.
Claim 3
Dependent Claim 50 words
A semiconductor memory device according to claim 1, wherein, when said volatile memory means are to be refreshed before a store operation, said timer output selection circuit supplies one of said timer outputs, the cycle of said one timer output selected being shortest among the cycles of said timer outputs.
Claim 4
Dependent Claim 29 words
A semiconductor memory device according to claim 1, wherein said timer output selection circuit receives a selfrefresh signal before receiving a store enable signal and a selfrecall enable signal.
Claim 5
Dependent Claim 57 words
A semiconductor memory device according to claim 3, wherein, when said selfrefresh signal is received before said store enable signal is active and said selfrecall enable signal is not active, said timer output selection circuit supplies one of said timer outputs, the cycle of said one timer output being shortest among the cycles of said timer outputs.
Claim 6
Dependent Claim 107 words
A semiconductor memory device comprising: a plurality of memory cells each of which comprises volatile memory means and nonvolatile memory means; and a plurality of word lines, said semiconductor memory device further comprising: an internal timer circuit for generating at least two timer outputs, the cycles of said timer outputs being different to each other; and a timer output selection circuit for receiving said timer outputs, and for selectively supplying one of said timer outputs to said word lines as a word line activation signal; each of said memory cells further comprises switch means for transferring data between said volatile memory means and said nonvolatile memory means.
Claim 7
Dependent Claim 107 words
A semiconductor memory device comprising: a plurality of memory cells each of which comprises volatile memory means and nonvolatile memory means; and a plurality of word lines, said semiconductor memory device further comprising: an internal timer circuit for generating at least two timer outputs, the cycles of said timer outputs being different to each other; and a timer output selection circuit for receiving said timer outputs, and for selectively supplying one of said timer outputs to said word lines as a word line activation signal; each of said memory cells further comprises switch means for transferring data between said volatile memory means and said nonvolatile memory means.

References Cited (Backward Citations)

US4747082A Cited
US4827453A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-14 1997-08-16 1998-02-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-14 2001-08-16 2002-02-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-14 2005-08-16 2006-02-15 $7700.00 Window Closed / Lapsed

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