US6137328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock phase correction circuit
Assignee: SK Hynix Inc
•
Filing: 1999-05-28
•
Granted: 2000-10-24
•
Expires: 2019-05-28
Abstract
Abstract A clock phase correction circuit for a semiconductor memory device reduces all lock ranges by using a half-mixer to a conventional delay locked loop (DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter. In order to achieve this objective, a track portion having a plurality of phase converters and one half-mixer is provided between an input terminal of external clock and an input terminal of a delay means of the conventional DLL circuit, and approaches the phase of the external clock to a phase of the feedback clock. A phase difference between the corrected signal and the feedback clock is then reduced by the conventional DLL circuit. As a result, lock time becomes shorter, and the magnitude of a jitter becomes reduced.
Inventors
- 👤 Jun Bae Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:44
CPC Classifications
H; H03; H03L; H03L7/00; H03K; H03K5/00; H03K5/13; H03K5/135; G; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
173 words
A clock phase correction circuit for receiving an external clock and generating an internal clock, the clock phase correction circuit comprising: a delay means for generating the internal clock; a model portion for receiving the internal clock generated from the delay means as an input and generating a feedback clock; a phase detector for receiving the external clock and the feedback clock generated from the model portion, comparing a phase of the external clock with a phase of the feedback clock, and generating a detection signal; a controller which is operated by the detection signal generated from the phase detector and transmits a control signal to the delay means to control the delay means; and a track portion which receives the external clock, an inverted external clock, and the feedback clock and reduces a phase difference between the external clock and the feedback clock, wherein the delay means which receives an output signal of the track portion as input is controlled by a control signal from the controller, and generates the internal clock.
Claim 2
Dependent Claim
173 words
A clock phase correction circuit for receiving an external clock and generating an internal clock, the clock phase correction circuit comprising: a delay means for generating the internal clock; a model portion for receiving the internal clock generated from the delay means as an input and generating a feedback clock; a phase detector for receiving the external clock and the feedback clock generated from the model portion, comparing a phase of the external clock with a phase of the feedback clock, and generating a detection signal; a controller which is operated by the detection signal generated from the phase detector and transmits a control signal to the delay means to control the delay means; and a track portion which receives the external clock, an inverted external clock, and the feedback clock and reduces a phase difference between the external clock and the feedback clock, wherein the delay means which receives an output signal of the track portion as input is controlled by a control signal from the controller, and generates the internal clock.
Claim 3
Dependent Claim
52 words
A clock phase correction circuit as set forth in claim 1, wherein the track portion includes a plurality of phase converters connected in series to each other, wherein the plurality of phase converters detect a phase of the feedback clock, and sequentially approach the external clock phase to the feedback clock phase.
Claim 4
Dependent Claim
99 words
A clock phase correction circuit as set forth in claim 1, wherein the track portion comprises: a plurality of phase converters being connected in series; and a half-mixer which receives a pair of output signals of the plurality of phase converters, the output signals having a different phase, and generates the internal clock that has a phase of intermediate value of a phase difference between the pair of output signals, wherein the plurality of phase converters detect a phase of the feedback clock, and sequentially approach a phase of the external clock to the phase of the feedback clock.
Claim 5
Dependent Claim
150 words
A clock phase correction circuit for receiving an external clock and generating an internal clock, the clock phase correction circuit comprising: a model portion for receiving the internal clock as an input, and generating a feedback clock; a plurality of phase converters connected in series, which receive the external clock, an inversion external clock of inverting the external clock, and the feedback clock, and reduce a phase difference between the external clock and the feedback clock; and a half-mixer which receives a pair of output signals of the plurality of phase converters, the output signals having a different phase, and generates the internal clock that has a phase of intermediate value of a phase difference between the pair of output signals, wherein the plurality of phase converters detect a phase of the feedback clock, and sequentially approach a phase of the external clock to the phase of the feedback clock.
Claim 6
Dependent Claim
150 words
A clock phase correction circuit for receiving an external clock and generating an internal clock, the clock phase correction circuit comprising: a model portion for receiving the internal clock as an input, and generating a feedback clock; a plurality of phase converters connected in series, which receive the external clock, an inversion external clock of inverting the external clock, and the feedback clock, and reduce a phase difference between the external clock and the feedback clock; and a half-mixer which receives a pair of output signals of the plurality of phase converters, the output signals having a different phase, and generates the internal clock that has a phase of intermediate value of a phase difference between the pair of output signals, wherein the plurality of phase converters detect a phase of the feedback clock, and sequentially approach a phase of the external clock to the phase of the feedback clock.
References Cited (Backward Citations)
US5295164A
Cited
US5544203A
Cited
US5337285A
Cited
US5440515A
Cited
US5440514A
Cited
US5740115A
Cited
US5796673A
Cited
US5708611A
Cited
US5629897A
Cited
US5666322A
Cited
WO1997040576A1
Cited
US5838630A
Cited
US5815427A
Cited
US5818788A
Cited
US5994934A
Cited
US6005426A
Cited
US6043694A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |