US6005426A
Expired / Lapsed
US
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Digital-type delay locked loop with expanded input locking range
Assignee: Via Technologies Inc
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Filing: 1998-05-06
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Granted: 1999-12-21
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Expires: 2018-05-06
Abstract
Abstract A low-jitter delay locked loop having an expanded phase locking range without the necessity of setting the initial delay is provided. The loop is to be supplied by a system clock and includes a pulse generator receiving the system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal, a delay device receiving the system clock for providing a delayed clock in response to a control signal, a frequency-reducing device for frequency-reducing the system clock into a first clock in response to the first pulse signal and frequency-reducing the delayed clock into a second clock in response to the second pulse signal, and a comparator for comparing the first and second clocks to generate the control signal.
Inventors
- 👤 Jyhfong Lin
- 👤 Hsin-Chieh Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:15
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/10
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
121 words
A delay locked loop adapted to be supplied by a system clock comprising: a pulse generator receiving said system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal; a delay device receiving said system clock for providing a delayed clock in response to a control signal; a frequency-reducing device electrically connected to said pulse generator for frequency-reducing said system clock into a first clock in response to said first pulse signal and frequency-reducing said delayed clock into a second clock in response to said second pulse signal; and a comparator electrically connected to said frequency-reducing device and said delay device for comparing said first and second clocks to generate said control signal.
Claim 2
Dependent Claim
121 words
A delay locked loop adapted to be supplied by a system clock comprising: a pulse generator receiving said system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal; a delay device receiving said system clock for providing a delayed clock in response to a control signal; a frequency-reducing device electrically connected to said pulse generator for frequency-reducing said system clock into a first clock in response to said first pulse signal and frequency-reducing said delayed clock into a second clock in response to said second pulse signal; and a comparator electrically connected to said frequency-reducing device and said delay device for comparing said first and second clocks to generate said control signal.
Claim 3
Dependent Claim
17 words
A delay locked loop according to claim 1 wherein said delay device is a clock delay array.
Claim 4
Dependent Claim
61 words
A delay locked loop according to claim 1 wherein said pulse generator includes: a reset element receiving said system clock for generating two clock signals one of which is said second pulse signal; and a buffer electrically connected to said reset and said frequency-reducing device for receiving the other one of said two clock signals and generating said first pulse signal.
Claim 5
Dependent Claim
15 words
A delay locked loop according to claim 3 wherein said reset is a D-type flip-flop.
Claim 6
Dependent Claim
17 words
A delay locked loop according to claim 3 wherein said buffer includes inverters of an even number.
Claim 7
Dependent Claim
24 words
A delay locked loop according to claim 3 wherein said first pulse signal has a time delay when compared to said second pulse signal.
Claim 8
Dependent Claim
16 words
A delay locked loop according to claim 1 wherein said frequency-reducing device is a frequency-dividing device.
Claim 9
Dependent Claim
72 words
A delay locked loop according to claim 7 wherein said frequency-dividing device includes: a first divider electrically connected to said pulse generator and said comparator for dividing said system clock to obtain said first clock in response to said first pulse signal; and a second divider electrically connected to said pulse generator and said comparator for dividing said delayed clock to obtain said second clock in response to said second pulse signal.
Claim 10
Dependent Claim
16 words
A delay locked loop according to claim 8 wherein said dividers are of the same specification.
Claim 11
Dependent Claim
21 words
A delay locked loop according to claim 8 wherein said dividers are D-type flip-flops for dividing the respective clock by 2.
Claim 12
Dependent Claim
56 words
A delay locked loop according to claim 1 wherein said comparator includes: a phase detector electrically connected to said frequency-reducing device for detecting a phase difference between said first and second clocks; and a counter electrically connected to said phase detector and said delay device for generating said control signal in response to said phase difference.
Claim 13
Dependent Claim
18 words
A delay locked loop according to claim 1, further comprising a clock generator for generating said system clock.
Claim 14
Dependent Claim
17 words
A delay locked loop according to claim 1, further comprising a trigger for providing said triggering signal.
Claim 15
Dependent Claim
91 words
A delay locking method comprising the following steps: a) providing a system clock, a delayed clock and a triggering signal; b) converting said system clock into a first pulse signal and a second pulse signal in response to said triggering signal; c) respectively frequency-reducing said system clock and said delayed clock into a first clock and a second clock having a phase difference respectively in response to said first pulse signal and said second pulse signal; and d) adjusting a delay degree of said delayed clock according to said phase difference.
Claim 16
Dependent Claim
91 words
A delay locking method comprising the following steps: a) providing a system clock, a delayed clock and a triggering signal; b) converting said system clock into a first pulse signal and a second pulse signal in response to said triggering signal; c) respectively frequency-reducing said system clock and said delayed clock into a first clock and a second clock having a phase difference respectively in response to said first pulse signal and said second pulse signal; and d) adjusting a delay degree of said delayed clock according to said phase difference.
Claim 17
Dependent Claim
42 words
A delay locking method according to claim 14, further comprising the following steps between said steps c) and d): c1) generating a control signal in response to said phase difference; and c2) adjusting said delay degree in response to said control signal.
Claim 18
Dependent Claim
49 words
A delay locking method according to claim 15 wherein said step b) further includes sub-steps of: b1) converting said system clock into two clock signals one of which is said second pulse signal; and b2) converting the other one of said two clock signals into said first pulse signal.
Claim 19
Dependent Claim
26 words
A delay locking method according to claim 16 wherein said the other clock signal is converted at a time delay after said system clock is converted.
Claim 20
Dependent Claim
18 words
A delay locking method according to claim 14 wherein said step b) is performed by a pulse generator.
Claim 21
Dependent Claim
18 words
A delay locking method according to claim 14 wherein said step c) is performed by two frequency dividers.
Claim 22
Dependent Claim
21 words
A delay locking method according to claim 14 wherein said step d) is performed by a comparator and a delay device.
Claim 23
Dependent Claim
18 words
A delay locking method according to claim 20 wherein said comparator includes a phase detector and a counter.
Claim 24
Dependent Claim
98 words
A delay locked loop adapted to be supplied by a system clock, a triggering signal and a delayed clock comprising: a pulse generator receiving said system clock for generating a first pulse signal and a second pulse signal in response to said triggering signal; and a frequency-reducing device electrically connected to said pulse generator for, respectively in response to said first pulse signal and said second pulse signal, respectively frequency-reducing said system clock and said delayed clock into a first clock and a second clock having a phase difference in response to which said delayed clock is delayed.
Claim 25
Dependent Claim
98 words
A delay locked loop adapted to be supplied by a system clock, a triggering signal and a delayed clock comprising: a pulse generator receiving said system clock for generating a first pulse signal and a second pulse signal in response to said triggering signal; and a frequency-reducing device electrically connected to said pulse generator for, respectively in response to said first pulse signal and said second pulse signal, respectively frequency-reducing said system clock and said delayed clock into a first clock and a second clock having a phase difference in response to which said delayed clock is delayed.
Claim 26
Dependent Claim
36 words
A delay locked loop according to claim 22, further comprising a comparator electrically connected to said frequency-reducing device for comparing said first and second clocks to obtain said phase difference for accordingly generating a control signal.
Claim 27
Dependent Claim
28 words
A delay locked loop according to claim 23, further comprising a delay device receiving said system clock for providing said delayed clock in response to said control signal.
Claim 28
Dependent Claim
26 words
A delay locked loop according to claim 22, further comprising a clock generator for generating said system clock and a trigger for providing said triggering signal.
References Cited (Backward Citations)
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