Integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal

Claim 2

An integrated-circuit device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; and a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal.

Claim 3

The integrated-circuit device as claimed in claim 1, wherein said control circuit comprises power-control-signal generating means for generating a power-control signal based on said timing to start receiving said first data signal, and said second clock-input circuit is turned on when receiving said power-control signal from said power-control-signal generating means.

Claim 4

The integrated-circuit device as claimed in claim 2, wherein said control circuit further comprises reception-control-signal generating means for generating a reception-control signal based on said timing to start receiving said first data signal, and said second data-input circuit starts receiving said second data signal based on said second clock signal when receiving said reception-control signal from said reception-control-signal generating means.

Claim 5

The integrated-circuit device as claimed in claim 3, wherein said reception-control-signal generating means generates said reception-control signal at a timing depending on a content of said first data signal.

Claim 6

The integrated-circuit device as claimed in claim 4, wherein said reception-control-signal generating means comprises: storage means for storing information; and means for adjusting a timing to generate said reception-control signal based on said information stored in said storage means.

Claim 7

The integrated-circuit device as claimed in claim 3, wherein said second clock signal has a pulse length of one unit time and changes from an intermediate voltage level to a first level which lasts for N unit times before changing to a second level, and wherein said reception-control-signal generating means generates said reception-control signal which lasts longer than one unit time and shorter than N+1 unit times.

Claim 8

The integrated-circuit device as claimed in claim 6, wherein said timing to start receiving said second data signal is when said second clock signal changes to said second level during a presence of said reception-control signal.

Claim 9

The integrated-circuit device as claimed in claim 3, further comprising: a predetermined number of latches each simultaneously holding a corresponding datum of a plurality of data which said second data-input circuit successively receives from said timing to start receiving said second data signal; and data reading means for reading said data from said latches by using a third clock signal.

Claim 10

The integrated-circuit device as claimed in claim 8, further comprising means for generating said third clock signal based on said first clock signal.

Claim 11

The integrated-circuit device as claimed in claim 8, further comprising an internal data bus, wherein said data reading means serially outputs each datum of said data to said internal data bus based on said third clock signal.

Claim 12

The integrated-circuit device as claimed in claim 1, further comprising: a clock-output circuit outputting a fourth clock signal; a data-output circuit outputting a fourth data signal in synchronism with said fourth clock signal; and clock generating means for generating said fourth clock signal based on said first clock signal such that said fourth clock signal has edges aligned in time with edges of said first clock signal.

Claim 13

The integrated-circuit device as claimed in claim 11, wherein said clock generating means comprises: internal-signal generating means for generating an internal signal; phase comparing means for comparing phases between said internal signal and said first clock signal to obtain a phase difference; and control means for controlling said internal-signal generating means to make said phase difference zero.

Claim 14

The integrated-circuit device as claimed in claim 12, wherein said clock generating means comprises a DLL (delay latched loop) circuit.

Claim 15

The integrated-circuit device as claimed in claim 13, wherein said clock generating means further comprises operation-control means for allowing the rest of said clock generating means to operate only when outputting said fourth data signal.

Claim 16

The integrated-circuit device as claimed in claim 1, wherein said control circuit comprises a latency setting circuit to which settings are made to determine a delay from a cycle to start receiving said first data signal to a cycle to start receiving said second data signal, and said second data-input circuit is turned on when receiving a power-control signal generated by said latency setting circuit.

Claim 17

The integrated-circuit device as claimed in claim 15, wherein said settings of said latency setting circuit are made according to a content of said first data signal.

Claim 18

The integrated-circuit device as claimed in claim 15, wherein said control circuit further comprises latency programming means for storing program data determining said delay, and makes said settings based on a content of said first data signal and said program data.

Claim 19

An integrated-circuit device comprising: a clock-output circuit sending out a first clock signal; a data-output circuit sending out a first-data signal in synchronism with said first clock signal; a clock-input circuit receiving a second clock signal; a data-input circuit receiving a second data signal in synchronism with said second clock signal; and a control circuit controlling a timing to start receiving said second data signal based on a timing to start sending out said first data signal.

Claim 20

An integrated-circuit device comprising: a clock-output circuit sending out a first clock signal; a data-output circuit sending out a first-data signal in synchronism with said first clock signal; a clock-input circuit receiving a second clock signal; a data-input circuit receiving a second data signal in synchronism with said second clock signal; and a control circuit controlling a timing to start receiving said second data signal based on a timing to start sending out said first data signal.

Claim 21

The integrated-circuit device as claimed in claim 18, wherein said control circuit comprises power-control-signal generating means for generating a power-control signal based on said timing to start sending out said first data signal, and wherein said clock-input circuit is turned on when receiving said power-control signal from said power-control-signal generating means.

Claim 22

The integrated-circuit device as claimed in claim 19, wherein said control circuit further comprises reception-control-signal generating means for generating a reception-control signal based on said timing to start sending out said first data signal, and wherein said data-input circuit starts receiving said second data signal based on said second clock signal when receiving said reception-control signal from said reception-control-signal generating means.

Claim 23

The integrated-circuit device as claimed in claim 20, wherein said reception-control-signal generating means generates said reception-control signal at a timing depending on a content of said first data signal.

Claim 24

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a memory core circuit into which said second data signal is written or from which said third data signal is read, depending on said first data signal, wherein said first clock-input circuit, said first data-input circuit, said second clock-input circuit, said second data-input circuit, said clock output circuit, said data output circuit, said clock generating means, and said memory core circuit are arranged on a chip, and said clock generating means is positioned at a general center of said chip.

Claim 25

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a memory core circuit into which said second data signal is written or from which said third data signal is read, depending on said first data signal, wherein said first clock-input circuit, said first data-input circuit, said second clock-input circuit, said second data-input circuit, said clock output circuit, said data output circuit, said clock generating means, and said memory core circuit are arranged on a chip, and said clock generating means is positioned at a general center of said chip.

Claim 26

The semiconductor memory device as claimed in claim 22, wherein said memory core circuit comprises a first memory core circuit and a second memory core circuit, and said clock generating means has a position between said first memory core circuit and said second memory core circuit on said chip.

Claim 27

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a plurality of memory core circuits into which said second data signal is written or from which said third data signal is read, depending on said first data signal, wherein said first clock-input circuit, said first data-input circuit, said second clock-input circuit, said second data-input circuit, said clock output circuit, said data output circuit, said clock generating means, and said plurality of memory core circuits are arranged on a chip, and said clock generating means is positioned between said plurality of memory core circuits.

Claim 28

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a plurality of memory core circuits into which said second data signal is written or from which said third data signal is read, depending on said first data signal, wherein said first clock-input circuit, said first data-input circuit, said second clock-input circuit, said second data-input circuit, said clock output circuit, said data output circuit, said clock generating means, and said plurality of memory core circuits are arranged on a chip, and said clock generating means is positioned between said plurality of memory core circuits.

Claim 29

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; and a memory core circuit storing said second data signal in response to said first data signal.

Claim 30

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; and a memory core circuit storing said second data signal in response to said first data signal.

Claim 31

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal, said control circuit including power-control-signal generating means for generating a power-control signal based on said timing to start receiving said first data signal, and including reception-control-signal generating means for generating a reception-control signal based on said timing to start receiving said first data signal, wherein said second clock-input circuit is turned on when receiving said power-control signal from said power-control-signal generating means, and said second data-input circuit starts receiving said second data signal based on said second clock signal when receiving said reception-control signal from said reception-control-signal generating means; a predetermined number of latches each simultaneously holding a corresponding datum of a plurality of data which said second data-input circuit successively receives from said timing to start receiving said second data signal; data reading means for reading said data from said latches by using a third clock signal; and a memory core circuit which stores said data.

Claim 32

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal, said control circuit including power-control-signal generating means for generating a power-control signal based on said timing to start receiving said first data signal, and including reception-control-signal generating means for generating a reception-control signal based on said timing to start receiving said first data signal, wherein said second clock-input circuit is turned on when receiving said power-control signal from said power-control-signal generating means, and said second data-input circuit starts receiving said second data signal based on said second clock signal when receiving said reception-control signal from said reception-control-signal generating means; a predetermined number of latches each simultaneously holding a corresponding datum of a plurality of data which said second data-input circuit successively receives from said timing to start receiving said second data signal; data reading means for reading said data from said latches by using a third clock signal; and a memory core circuit which stores said data.

Claim 33

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a memory core circuit from which said third data signal is read out.

Claim 34

A semiconductor memory device comprising: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal; a clock-output circuit outputting a third clock signal; a data-output circuit outputting a third data signal in synchronism with said third clock signal; clock generating means for generating said third clock signal based on said first clock signal such that said third clock signal has edges aligned in time with edges of said first clock signal; and a memory core circuit from which said third data signal is read out.

Claim 35

An integrated-circuit system comprising: a first integrated circuit; and a second integrated circuit, wherein said first integrated circuit comprises: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a first clock-output circuit outputting a third clock signal; a first data-output circuit outputting a third data signal in synchronism with said third clock signal; and a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal, and wherein said second integrated circuit comprises: a second clock-output circuit sending out said first clock signal; a second data-output circuit sending out said first data signal in synchronism with said first clock signal; a third clock-output circuit sending out said second clock signal; a third data-output circuit sending out said second data signal in synchronism with said second clock signal; a third clock-input circuit receiving said third clock signal; a third data-input circuit receiving said third data signal in synchronism with said third clock signal; and a control circuit controlling a timing to start receiving said third data signal based on a timing to start sending out said first data signal.

Claim 36

An integrated-circuit system comprising: a first integrated circuit; and a second integrated circuit, wherein said first integrated circuit comprises: a first clock-input circuit receiving a first clock signal; a first data-input circuit receiving a first data signal in synchronism with said first clock signal; a second clock-input circuit receiving a second clock signal; a second data-input circuit receiving a second data signal in synchronism with said second clock signal; a first clock-output circuit outputting a third clock signal; a first data-output circuit outputting a third data signal in synchronism with said third clock signal; and a control circuit controlling a timing to start receiving said second data signal based on a timing to start receiving said first data signal, and wherein said second integrated circuit comprises: a second clock-output circuit sending out said first clock signal; a second data-output circuit sending out said first data signal in synchronism with said first clock signal; a third clock-output circuit sending out said second clock signal; a third data-output circuit sending out said second data signal in synchronism with said second clock signal; a third clock-input circuit receiving said third clock signal; a third data-input circuit receiving said third data signal in synchronism with said third clock signal; and a control circuit controlling a timing to start receiving said third data signal based on a timing to start sending out said first data signal.