US6744094B2
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Floating gate transistor with horizontal gate layers stacked next to vertical body
Assignee: Micron Technology Inc
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Filing: 2001-08-24
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Granted: 2004-06-01
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Expires: 2021-08-24
Abstract
Abstract Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F 2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:13
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6894; H10D64/00; H10D64/01; H10D64/031; H10D64/035; G11C16/0416
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
92 words
A floating gate transistor comprising: a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form a source region, a body region and a drain region of a floating gate transistor; a floating gate along one side of the pillar, wherein the floating gate overlaps the body region in a horizontal direction; and a control gate overlaying the floating gate, wherein the portion of the control gate overlapping the floating gate does not overlap the body region in either the horizontal direction or a vertical direction.
Claim 2
Dependent Claim
92 words
A floating gate transistor comprising: a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form a source region, a body region and a drain region of a floating gate transistor; a floating gate along one side of the pillar, wherein the floating gate overlaps the body region in a horizontal direction; and a control gate overlaying the floating gate, wherein the portion of the control gate overlapping the floating gate does not overlap the body region in either the horizontal direction or a vertical direction.
Claim 3
Dependent Claim
23 words
The floating gate transistor of claim 1 , wherein charges are selectively stored in the floating gate in programming the floating gate transistor.
Claim 4
Dependent Claim
15 words
The floating gate transistor of claim 1 , wherein the pillar is formed by etching.
Claim 5
Dependent Claim
36 words
The floating gate transistor of claim 1 , wherein an absence or a presence of stored charges on the floating gate determines a conductivity state of the transistor between the source region and the drain region.
Claim 6
Dependent Claim
16 words
The floating gate transistor of claim 1 , wherein the substrate is a bulk semiconductor substrate.
Claim 7
Dependent Claim
15 words
The floating gate transistor of claim 1 , wherein the substrate is a silicon-on-insulator substrate.
Claim 8
Dependent Claim
20 words
The floating gate transistor of claim 2 , wherein hot electron injection is used to program the floating gate transistor.
Claim 9
Dependent Claim
19 words
The floating gate transistor of claim 2 , wherein Fowler-Nordheim tunneling is used to program the floating gate transistor.
Claim 10
Dependent Claim
113 words
An array of floating gate transistors comprising: a plurality of semiconductor stacks arranged in rows and in columns, wherein each stack forms source, body, and drain regions of a respective floating gate transistor; a plurality of floating gates in trenches between the columns of semiconductor stacks, wherein the floating gates are separated from respective sides of the semiconductor stacks by a gate dielectric; and a plurality of control gates overlaying the respective floating gates and separated from the respective floating gates by an intergate dielectric, wherein the control gates in vertical alignment with the respective floating gates do not align with the body regions in either a horizontal direction or a vertical direction.
Claim 11
Dependent Claim
113 words
An array of floating gate transistors comprising: a plurality of semiconductor stacks arranged in rows and in columns, wherein each stack forms source, body, and drain regions of a respective floating gate transistor; a plurality of floating gates in trenches between the columns of semiconductor stacks, wherein the floating gates are separated from respective sides of the semiconductor stacks by a gate dielectric; and a plurality of control gates overlaying the respective floating gates and separated from the respective floating gates by an intergate dielectric, wherein the control gates in vertical alignment with the respective floating gates do not align with the body regions in either a horizontal direction or a vertical direction.
Claim 12
Dependent Claim
23 words
The array of claim 9 , wherein etching is used to form the plurality of semiconductor stacks which extend vertically from a substrate.
Claim 13
Dependent Claim
43 words
The array of claim 9 , wherein each of the respective floating gate transistors extend outwardly from a substrate with a source region formed proximally to the substrate, a body region above the source region, and a drain region above the body region.
Claim 14
Dependent Claim
33 words
The array of claim 11 , wherein two floating gates lie adjacent to each other in each trench between the columns of semiconductor stacks, and one control gate overlays the adjacent floating gates.
Claim 15
Dependent Claim
28 words
The array of claim 11 , wherein one floating gate lie in each trench between the columns of semiconductor stacks, and one control gate overlays the floating gate.
Claim 16
Dependent Claim
39 words
The array of claim 11 , wherein two floating gates lie adjacent to each other in each trench between the columns of the semiconductor stacks, and two corresponding control gates lie adjacent to each other above the floating gates.
Claim 17
Dependent Claim
60 words
The array of claim 12 , wherein the array is a memory cell array with the source regions of common rows electrically connected to be first input selection lines, the control gates electrically connected along the direction of the columns to be second input selection lines, and the drain regions of common columns electrically connected to be output data lines.
Claim 18
Dependent Claim
69 words
The array of claim 13 , wherein the array is a logic array with the source regions of a common column electrically coupled to be selection lines during programming of the logic array, the control gates electrically coupled along the direction of the columns to be inputs to the logic array, and the drain regions of a common row electrically coupled to be output lines of the logic array.
Claim 19
Dependent Claim
45 words
The array of claim 14 , wherein the array is a field programmable logic array with the source regions of a common column electrically interconnected, the drain regions of a common row electrically interconnected, and the control gates interconnected along the direction of the columns.
Claim 20
Dependent Claim
23 words
The array of claim 15 , wherein charges are stored in the floating gates to represent respective data in the memory cell array.
Claim 21
Dependent Claim
28 words
The array of claim 18 , wherein hot electron injection is used to selectively place charges in the respective floating gates, thereby programming the respective floating gate transistors.
Claim 22
Dependent Claim
201 words
A floating gate transistor that is fabricated upon a substrate, the floating gate transistor comprising: a first conductivity type semiconductor pillar formed upon the substrate, wherein the pillar has top and side surfaces; a first source/drain region of a second conductivity type formed in a portion of the pillar that is proximal to an interface between the pillar and the substrate; a second source/drain region of a second conductivity type formed in a portion of the pillar that is distal to the substrate and separated from the first source/drain region; a gate dielectric formed on at least a portion of one side surface of the pillar; a floating gate substantially adjacent to a body region defined by the separation between the first source/drain region and the second source/drain region, wherein the floating gate is separated from the body region by the gate dielectric; an intergate dielectric formed on a top surface of the floating gate; and a control gate substantially overlaying the floating gate and insulated therefrom by the intergate dielectric, such that the portion of the control gate above the floating gate does not overlap the body region next to the floating gate in either a horizontal or vertical direction.
Claim 23
Dependent Claim
201 words
A floating gate transistor that is fabricated upon a substrate, the floating gate transistor comprising: a first conductivity type semiconductor pillar formed upon the substrate, wherein the pillar has top and side surfaces; a first source/drain region of a second conductivity type formed in a portion of the pillar that is proximal to an interface between the pillar and the substrate; a second source/drain region of a second conductivity type formed in a portion of the pillar that is distal to the substrate and separated from the first source/drain region; a gate dielectric formed on at least a portion of one side surface of the pillar; a floating gate substantially adjacent to a body region defined by the separation between the first source/drain region and the second source/drain region, wherein the floating gate is separated from the body region by the gate dielectric; an intergate dielectric formed on a top surface of the floating gate; and a control gate substantially overlaying the floating gate and insulated therefrom by the intergate dielectric, such that the portion of the control gate above the floating gate does not overlap the body region next to the floating gate in either a horizontal or vertical direction.
Claim 24
Dependent Claim
28 words
The floating gate transistor of claim 20 , wherein electrical charges in the floating gate controls electrical conduction between the first source/drain region and the second source/drain region.
Claim 25
Dependent Claim
35 words
The floating gate transistor of claim 20 , wherein the floating gate transistor is a data storage element in a programmable memory array with the data represented by charges stored in the respective floating gates.
References Cited (Backward Citations)
EP0236676A2
Cited
US5510730A
Cited
EP0498642A1
Cited
US5386132A
Cited
US5379255A
Cited
US5460988A
Cited
US5696008A
Cited
US6040210A
Cited
US5874760A
Cited
US6143636A
Cited
US5909618A
Cited
US6150687A
Cited
US5973356A
Cited
US5936274A
Cited
US6072209A
Cited
US6104061A
Cited
US5973352A
Cited
US6124729A
Cited
US5991225A
Cited
US6153468A
Cited
US6486027B1
Cited
US20020195649A1
Cited
US6134175A
Cited
US6208164B1
Cited
US6580124B1
Cited
US20020142546A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-06-01 | 2007-12-01 | 2008-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-06-01 | 2011-12-01 | 2012-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-06-01 | 2015-12-01 | 2016-06-01 | $7700.00 | Window Closed / Lapsed |