Erasable programmable read only memory using floating gate field effect transistors

Claim 2

An erasable programmable read only memory (EPROM) having a plurality of memory cell field effect transistors (FETs) arranged in a matrix on a semiconductor substrate (1), each memory cell FET comprising: a floating gate (8), for storing voltage thereon and controlling the conductivity of the memory cell FET; a first gate insulation film (3), provided between the floating gate and the substrate for insulating the floating gate from the from the substrate; a control gate (7) positioned over the floating gate, for controlling the voltage of the floating gate; a second insulation film (6) provided between the floating gate and the control gate, for insulating the floating gate from the control gate; and device separation regions (13) provided on both sides of the floating gate in the gate width direction, for separating the memory cell FET from adjacent memory cell FETs an both those sides, wherein the floating gate is positioned underneath the control gate, the width of the control gate being equal to the length of the floating gate, and the floating gate and device separation regions being aligned side by side at the edges of the floating gate on its gate width sides.

Claim 3

An EPROM as claimed in claim 1, wherein each memory cell FET further comprises a thin insulation film (12˝) covering side edges of the floating gate (8) and the control gate (7).

Claim 4

An EPROM as claimed in claim 1 or 2, wherein the floating gate (8) and the control gate (7) are of polysilicon.

Claim 5

An EPROM as claimed in claim 1, 2 or 3, wherein the substrate (1) is of silicon, the first gate insulation film (3), the second gate insulation film (6), and the thin insulation film (12˝) are of silicon dioxide.

Claim 6

An EPROM as claimed in claim 1 or 2, wherein the floating gate (8) and the control gate (7) are of metal silicide.

Claim 7

A process for fabricating an erasable programmable read only memory (EPROM) having a plurality of memory cell field effect transistors (FETs) arranged in a matrix on a semiconductor substrate, the process comprising: (a) forming successively on a semiconductor substrate (1), having a first conductivity type, a first gate insulating film (3) and a first conductive layer (PA,5); (b) forming by photolithography a plurality of parallel device separation grooves (11) extending in the gate length direction of the memory cell FETs to be fabricated, the spacing between the device separation grooves (11) being equal to the gate width of the memory cell FETs to be fabricated, and the depth of the grooves (11) being such that they penetrate through the first conductive layer and the first gate insulation film into the substrate (1); (c) forming a thick insulation layer (12) to bury the device separation grooves; (d) removing parts of the thick insulation layer to expose the surface of the first conductive layer; (e) forming a second gate insulation film (6) over the exposed surface of the first conductive layer and subsequently forming a second conductive layer (PB,7) thereover; (f) etching off the second conductive layer to leave parallel stripes (7) of the material of that layer arranged orthogonally of the device separation grooves, the spacing between the stripes being equal to the spacing between the memory cell FETs to be fabricated, and the width of the stripes being equal to the gate length of the memory cell FETs to be fabricated, and then etching off successively the second gate insulating film, the first conductive layer and the first gate insulation film to expose the semiconductor substrate, using the parallel stripes (7) as a mask; and (g) doping impurities, having conductivity type opposite to that of the semiconductor substrate, into the exposed semiconductor substrate to form source (9) and drain regions (10) of the memory cell FETs to be fabricated.

Claim 8

A process for fabricating an erasable programmable read only memory (EPROM) having a plurality of memory cell field effect transistors (FETs) arranged in a matrix on a semiconductor substrate, the process comprising: (a) forming successively on a semiconductor substrate (1), having a first conductivity type, a first gate insulating film (3) and a first conductive layer (PA,5); (b) forming by photolithography a plurality of parallel device separation grooves (11) extending in the gate length direction of the memory cell FETs to be fabricated, the spacing between the device separation grooves (11) being equal to the gate width of the memory cell FETs to be fabricated, and the depth of the grooves (11) being such that they penetrate through the first conductive layer and the first gate insulation film into the substrate (1); (c) forming a thick insulation layer (12) to bury the device separation grooves; (d) removing parts of the thick insulation layer to expose the surface of the first conductive layer; (e) forming a second gate insulation film (6) over the exposed surface of the first conductive layer and subsequently forming a second conductive layer (PB,7) thereover; (f) etching off the second conductive layer to leave parallel stripes (7) of the material of that layer arranged orthogonally of the device separation grooves, the spacing between the stripes being equal to the spacing between the memory cell FETs to be fabricated, and the width of the stripes being equal to the gate length of the memory cell FETs to be fabricated, and then etching off successively the second gate insulating film, the first conductive layer and the first gate insulation film to expose the semiconductor substrate, using the parallel stripes (7) as a mask; and (g) doping impurities, having conductivity type opposite to that of the semiconductor substrate, into the exposed semiconductor substrate to form source (9) and drain regions (10) of the memory cell FETs to be fabricated.

Claim 9

A process as claimed in claim 6, further comprising: (b′) between steps (b) and (c), forming a thin insulation film (12′) over the surface exposed at the conclusion of step (b); (f′) between steps (f) and (g), forming a thin insulation film (12˝) over the surface exposed at the conclusion of step (f).

Claim 10

A process as claimed in claim 6 or 7, wherein the substrate (1) is of silicon, and the first gate insulation film (3) and the second gate insulation film (6), and the thin insulation films (12′,12˝) where provided, are of silicon dioxide, formed by thermal oxidation.

Claim 11

A process as claimed in claim 6, 7 or 8, wherein the first (PA,5) and second (PB,7) conductive layers are of polysilicon formed by chemical vapour deposition.

Claim 12

A process as claimed in claim 6, 7, 8 or 9, wherein step (d) is accomplished by reactive ion etching.

Claim 13

A process as claimed in claim 6, 7, 8 or 9, wherein step (d) is accomplished by mechanical polishing.

Claim 14

A process as claimed in claim 6, 7, 8, 9 or 10, wherein the etching processes employed in steps (b) and (f) are reactive ion etching processes.

Claim 15

A process as claimed in any one of claims 6 to 12, wherein step (c) is a chemical vapour deposition process and the thick insulation layer is a silicon dioxide layer.