Patent US6541320B2 successfully refreshed from Google Patents.
US6541320B2
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Method to controllably form notched polysilicon gate structures
Assignee: International Business Machines Corp
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Filing: 2001-08-10
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Granted: 2003-04-01
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Expires: 2021-08-10
Abstract
Abstract A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.
Inventors
- 👤 Jeffrey Brown
- 👤 Richard Wise
- 👤 Hongwen Yan
- 👤 Qingyun Yang
- 👤 Chienfan Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:59
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0179; H10D84/02; H10D84/03; H10D84/038; H10P50/71
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
148 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer having a first thickness on a surface of a gate dielectric; (b) forming a patterned mask over a portion of said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness; (d) forming a passivating film over at least exposed vertical portions of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; and (e) etching said gate conductor layer having reduced thickness and said conductor layer protected by said patterned mask to form undercut notches within said gate conductor layer at lower corners of said gate conductor layer that is beneath said patterned mask and said passivating film.
Claim 2
Independent Claim
148 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer having a first thickness on a surface of a gate dielectric; (b) forming a patterned mask over a portion of said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness; (d) forming a passivating film over at least exposed vertical portions of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; and (e) etching said gate conductor layer having reduced thickness and said conductor layer protected by said patterned mask to form undercut notches within said gate conductor layer at lower corners of said gate conductor layer that is beneath said patterned mask and said passivating film.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said gate conductor layer is formed by a deposition process.
Claim 4
Dependent Claim
43 words
The method of claim 1 wherein said gate conductor layer is a conductive material selected from the group consisting of elemental metals, alloys of elemental metals, silicides of elemental metals, nitrides of elemental metals, doped or undoped polysilicon and combinations or multilayers thereof.
Claim 5
Dependent Claim
15 words
The method of claim 3 wherein said gate conductive layer is comprised of doped polysilicon.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein said gate dielectric is an oxide, nitride, oxynitride or combinations and multilayers thereof.
Claim 7
Dependent Claim
18 words
The method of claim 1 wherein said gate dielectric is formed on a surface of a semiconductor substrate.
Claim 8
Dependent Claim
16 words
The method of claim 1 wherein said patterned mask is formed by deposition, lithography and etching.
Claim 9
Dependent Claim
21 words
The method of claim 1 wherein said patterned mask is comprised of an oxide, nitride, oxynitride or combinations and multilayers thereof.
Claim 10
Dependent Claim
21 words
The method of claim 1 wherein said patterned mask is comprised of a photoresist which is formed by deposition and lithography.
Claim 11
Dependent Claim
13 words
The method of claim 1 wherein step (c) comprises an anisotropic etching process.
Claim 12
Dependent Claim
17 words
The method of claim 10 wherein said anisotropic etching process includes the use of a halogen-containing plasma.
Claim 13
Dependent Claim
13 words
The method of claim 11 wherein said halogen-containing plasma comprises HBr/O 2 .
Claim 14
Dependent Claim
31 words
The method of claim 1 wherein said passivating layer is a material that is capable of adhering to said exposed vertical sidewalls and is resistant to removal by etching step (e).
Claim 15
Dependent Claim
22 words
The method of claim 1 wherein said C-containing film comprises C and at least one of Cl, Br, Fl, O, or H.
Claim 16
Dependent Claim
22 words
The method of claim 1 wherein said Si-containing film comprises Si and at least one of Cl, Br, Fl, O, or H.
Claim 17
Dependent Claim
24 words
The method of claim 1 wherein said Si—C-containing film comprises Si and C, and at least one of Cl, Br, Fl, O, or H.
Claim 18
Dependent Claim
15 words
The method of claim 1 wherein said passivating film is formed by a deposition process.
Claim 19
Dependent Claim
24 words
The method of claim 1 wherein said passivating film is also formed on exposed horizontal surfaces of said gate conductor layer of reduced thickness.
Claim 20
Dependent Claim
21 words
The method of claim 18 wherein said passivating film on said exposed horizontal surfaces is removed by an anisotropic etching process.
Claim 21
Dependent Claim
13 words
The method of claim 1 wherein step (e) includes an isotropic etching process.
Claim 22
Dependent Claim
31 words
The method of claim 20 wherein said isotropic etching process includes a high pressure HBr/Cl 2 /O 2 /N 2 plasma or a plasma that does not include Cl 2 .
Claim 23
Independent Claim
154 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer on a gate dielectric layer, said gate conductor layer having a first thickness; (b) forming a patterned mask over said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness; (d) depositing a passivating film on exposed surfaces of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; (e) removing said passivating film from horizontal portions of said gate conductor layer; and (f) selectively etching said gate conductor layer to remove said gate conductor layer from regions not protected by said patterned mask, thereby forming undercut notches within said gate conductor layer at corner locations where said gate conductor meets said gate dielectric layer.
Claim 24
Independent Claim
154 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer on a gate dielectric layer, said gate conductor layer having a first thickness; (b) forming a patterned mask over said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness; (d) depositing a passivating film on exposed surfaces of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; (e) removing said passivating film from horizontal portions of said gate conductor layer; and (f) selectively etching said gate conductor layer to remove said gate conductor layer from regions not protected by said patterned mask, thereby forming undercut notches within said gate conductor layer at corner locations where said gate conductor meets said gate dielectric layer.
Claim 25
Independent Claim
124 words
A method of forming a plurality of n-type and p-type notched gates on a single wafer comprising the steps of: (a) forming a gate conductor layer having a first thickness on a gate dielectric; (b) forming a patterned mask over a portion of said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness, (c) forming a passivating film over at least vertical portions of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; and (d) forming undercut notches within said gate conductor layer at lower corners of said gate conductor layer.
Claim 26
Independent Claim
124 words
A method of forming a plurality of n-type and p-type notched gates on a single wafer comprising the steps of: (a) forming a gate conductor layer having a first thickness on a gate dielectric; (b) forming a patterned mask over a portion of said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness, (c) forming a passivating film over at least vertical portions of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; and (d) forming undercut notches within said gate conductor layer at lower corners of said gate conductor layer.
Claim 27
Independent Claim
162 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer on a gate dielectric, said gate conductor layer having a first thickness; (b) patterning a mask over said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said mask to a reduced thickness, wherein said reduced thickness is greater than zero and less than said first thickness; (d) depositing a passivating film on exposed surfaces of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; (e) removing said passivating film from horizontal portions of said gate conductor layer using an anisotropic etch; and (f) selectively etching said gate conductor layer to remove said gate conductor layer from all regions not protected by said mask and said passivating film, thereby forming undercut notches within said gate conductor layer at corner locations where said gate conductor meets said gate dielectric.
Claim 28
Independent Claim
162 words
A method of forming a notched gate structure comprising the steps of: (a) forming a gate conductor layer on a gate dielectric, said gate conductor layer having a first thickness; (b) patterning a mask over said gate conductor layer; (c) etching said gate conductor layer in regions not protected by said mask to a reduced thickness, wherein said reduced thickness is greater than zero and less than said first thickness; (d) depositing a passivating film on exposed surfaces of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof; (e) removing said passivating film from horizontal portions of said gate conductor layer using an anisotropic etch; and (f) selectively etching said gate conductor layer to remove said gate conductor layer from all regions not protected by said mask and said passivating film, thereby forming undercut notches within said gate conductor layer at corner locations where said gate conductor meets said gate dielectric.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-31 | 2006-09-30 | 2007-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-31 | 2010-09-30 | 2011-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-31 | 2014-09-30 | 2015-04-01 | $7700.00 | Window Closed / Lapsed |