Patent US1417931A successfully refreshed from Google Patents.
Patent US2371039A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5866473A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a polysilicon gate having a dimension below the photolithography limitation

Assignee: GlobalFoundries Inc
•
Filing: 1997-10-31
•
Granted: 1999-02-02
•
Expires: 2017-10-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical diffraction in photolithography. The method includes forming a polysilicon gate structure on a gate oxide layer, forming a nitrogen-doped layer on the polysilicon gate structure, forming selected depth oxide sidewalls on the polysilicon gate structure and etching the nitrogen-doped layer and the oxide sidewalls.

Inventors

  • 👤 Qi Xiang
  • 👤 Ming-Ren Lin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 19:13
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10P30/208

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 67 words
A method of manufacturing an MOS transistor comprising: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon gate structure on the gate oxide layer; forming a nitrogen-doped layer in a top surface of the polysilicon gate structure; forming an oxide layer on the polysilicon gate structure to a selected depth; removing the nitrogen-doped layer; and removing the oxide layer from the polysilicon gate structure.
Claim 2
Independent Claim 67 words
A method of manufacturing an MOS transistor comprising: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon gate structure on the gate oxide layer; forming a nitrogen-doped layer in a top surface of the polysilicon gate structure; forming an oxide layer on the polysilicon gate structure to a selected depth; removing the nitrogen-doped layer; and removing the oxide layer from the polysilicon gate structure.
Claim 3
Dependent Claim 15 words
The method of claim 1 wherein forming a nitrogen-doped layer is accomplished by nitrogen implantation.
Claim 4
Dependent Claim 28 words
The method of claim 2 wherein the nitrogen implantation is accomplished at a dosage in the range of 10 14 to 10 15 ions per cm 2 .
Claim 5
Dependent Claim 23 words
The method of claim 3 wherein the nitrogen implantation is accomplished at an energy level in the range of 5 to 15 KeV.

References Cited (Backward Citations)

US5476802A Cited
US5759901A Cited
US5750435A Cited
US5750430A Cited
US5712173A Cited
US5786256A Cited
US5739064A Cited
US5776821A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-02-01 2002-08-03 2003-02-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-02-01 2006-08-03 2007-02-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-02-01 2010-08-03 2011-02-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag