Fabrication method for sub-half micron CMOS transistor

Claim 1

A method for the fabrication of a semi-conductor device comprising the steps of: (a) implanting a substrate with impurities of a first conductivity type to form an active region surrounded by an isolation region; (b) implanting, before formation of a gate oxide layer region, and before formation of a gate electrode, impurities of said first conductivity type to form a punch-through barrier region of said first conductivity type beneath the surface of said substrate such that a substantial portion of the barrier region is located below the gate electrode once the gate electrode has been formed, said barrier region having impurities of a first concentration; (c) forming a gate oxide layer region on a central portion of the active surface area over said barrier region; (d) forming a gate electrode over said gate oxide layer region; (e) implanting impurities of a first concentration into said substrate to form a first set of relatively low impurity concentration (LDD) regions in said substrate after formation of said gate electrode, the LDD region implant step being aligned by the gate electrode; (f) a first set of sidewall spacers over said relatively low impurity concentration (LDD) regions; (g) thereafter implanting impurities of a second concentration greater than said first concentration into said substrate, to form contiguous relatively moderate impurity concentration (MDD) regions in said substrate, horizontally adjacent to said relatively low impurity concentration (LDD) regions, the MDD region implant being aligned by the first set of sidewall spacers; (h) thereafter forming a second set of sidewall spacers adjacent to said first set of sidewall spacers such that said first set of sidewall spacers are interposed between said second set of sidewall spacers and said gate electrode; (i) implanting, after the formation of said second set of sidewall spacers, impurities of a third concentration greater than said second concentration into said substrate to form relatively high impurity concentration regions (HDD) in said substrate, the MDD region implantation step being aligned with said second set of sidewall spacers; and, (j) implanting impurities into said substrate to form co-implant regions, co-implant region being vertically adjacent to and under said HDD region in said substrate, the co-implant implantation step being aligned with the second set of sidewall spacers; wherein the LDD region, MDD region, HDD region and the co-implant region implant steps form source and drain impurity regions, said source and drain impurity regions being spaced apart from each other at opposite ends of said gate electrode with a conduction channel region therebetween and wherein said co-implant region and HDD regions cause the source and drain impurity regions to be vertically graded.

Claim 2

A method for the fabrication of a semi-conductor device comprising the steps of: (a) implanting a substrate with impurities of a first conductivity type to form an active region surrounded by an isolation region; (b) implanting, before formation of a gate oxide layer region, and before formation of a gate electrode, impurities of said first conductivity type to form a punch-through barrier region of said first conductivity type beneath the surface of said substrate such that a substantial portion of the barrier region is located below the gate electrode once the gate electrode has been formed, said barrier region having impurities of a first concentration; (c) forming a gate oxide layer region on a central portion of the active surface area over said barrier region; (d) forming a gate electrode over said gate oxide layer region; (e) implanting impurities of a first concentration into said substrate to form a first set of relatively low impurity concentration (LDD) regions in said substrate after formation of said gate electrode, the LDD region implant step being aligned by the gate electrode; (f) a first set of sidewall spacers over said relatively low impurity concentration (LDD) regions; (g) thereafter implanting impurities of a second concentration greater than said first concentration into said substrate, to form contiguous relatively moderate impurity concentration (MDD) regions in said substrate, horizontally adjacent to said relatively low impurity concentration (LDD) regions, the MDD region implant being aligned by the first set of sidewall spacers; (h) thereafter forming a second set of sidewall spacers adjacent to said first set of sidewall spacers such that said first set of sidewall spacers are interposed between said second set of sidewall spacers and said gate electrode; (i) implanting, after the formation of said second set of sidewall spacers, impurities of a third concentration greater than said second concentration into said substrate to form relatively high impurity concentration regions (HDD) in said substrate, the MDD region implantation step being aligned with said second set of sidewall spacers; and, (j) implanting impurities into said substrate to form co-implant regions, co-implant region being vertically adjacent to and under said HDD region in said substrate, the co-implant implantation step being aligned with the second set of sidewall spacers; wherein the LDD region, MDD region, HDD region and the co-implant region implant steps form source and drain impurity regions, said source and drain impurity regions being spaced apart from each other at opposite ends of said gate electrode with a conduction channel region therebetween and wherein said co-implant region and HDD regions cause the source and drain impurity regions to be vertically graded.

Claim 12

A method for fabricating a dual well semi-conductor device, comprising the steps of: (a) providing a substrate, forming in said substrate at least one well region, said at least one well region having an active surface area; (b) forming a gate insulating layer and a gate electrode over said gate insulating layer on a central portion of the active surface area; (c) implanting impurities of a first concentration into said substrate to form relatively low impurity concentration (LDD) regions, the LDD region implantation being aligned by the gate electrode; (d) forming a first set of sidewall spacers adjacent to said gate electrode; (e) thereafter implanting impurities of a second concentration greater than said first concentration into said substrate, to form contiguous relatively moderate impurity concentration (MDD) regions in said substrate, horizontally adjacent to said relatively low impurity concentration (LDD) regions, the MDD region implantation being aligned by the first set of sidewall spacers; (f) forming a second set of sidewall spacers adjacent to said first set of sidewall spacers such that said first set of sidewall spacers are interposed between said second set of sidewall spacers and said gate electrode; (g) implanting, after the formation of said second set of sidewall spacers, impurities a third concentration greater than said second concentration into said substrate to form relatively high impurity concentration regions (HDD) in said substrate, horizontally adjacent to said relatively moderate impurity concentration (MDD) regions and lying outside said gate electrode outside said second set of sidewall spacers, the HDD region implantation being aligned by the second set of sidewall spacers; (h) implanting impurities of a lower dose than the HDD region into said substrate to form a co-implant region, vertically adjacent to and under said HDD region in said substrate, the co-implant region being aligned by the second set of sidewall spacers; and wherein the LDD region, MDD region, HDD region and the co-implant region implant steps form source and drain impurity regions, said source and drain impurity regions being spaced apart from each other at opposite ends of said gate electrode with a conduction channel region therebetween; and wherein said co-implant region and HDD region forming a vertically graded source/drain region.

Claim 13

A method for fabricating a dual well semi-conductor device, comprising the steps of: (a) providing a substrate, forming in said substrate at least one well region, said at least one well region having an active surface area; (b) forming a gate insulating layer and a gate electrode over said gate insulating layer on a central portion of the active surface area; (c) implanting impurities of a first concentration into said substrate to form relatively low impurity concentration (LDD) regions, the LDD region implantation being aligned by the gate electrode; (d) forming a first set of sidewall spacers adjacent to said gate electrode; (e) thereafter implanting impurities of a second concentration greater than said first concentration into said substrate, to form contiguous relatively moderate impurity concentration (MDD) regions in said substrate, horizontally adjacent to said relatively low impurity concentration (LDD) regions, the MDD region implantation being aligned by the first set of sidewall spacers; (f) forming a second set of sidewall spacers adjacent to said first set of sidewall spacers such that said first set of sidewall spacers are interposed between said second set of sidewall spacers and said gate electrode; (g) implanting, after the formation of said second set of sidewall spacers, impurities a third concentration greater than said second concentration into said substrate to form relatively high impurity concentration regions (HDD) in said substrate, horizontally adjacent to said relatively moderate impurity concentration (MDD) regions and lying outside said gate electrode outside said second set of sidewall spacers, the HDD region implantation being aligned by the second set of sidewall spacers; (h) implanting impurities of a lower dose than the HDD region into said substrate to form a co-implant region, vertically adjacent to and under said HDD region in said substrate, the co-implant region being aligned by the second set of sidewall spacers; and wherein the LDD region, MDD region, HDD region and the co-implant region implant steps form source and drain impurity regions, said source and drain impurity regions being spaced apart from each other at opposite ends of said gate electrode with a conduction channel region therebetween; and wherein said co-implant region and HDD region forming a vertically graded source/drain region.