US5489543A
Expired / Lapsed
US
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Method of forming a MOS device having a localized anti-punchthrough region
Assignee: United Microelectronics Corp
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Filing: 1994-12-01
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Granted: 1996-02-06
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Expires: 2014-12-01
Abstract
Abstract A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/0217; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D30/60; H10D30/601
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
151 words
A method of forming a MOS device having a localized anti-punchthrough region, comprising the steps of: (a) providing a silicon substrate doped with impurities of a first conductivity type and having a predetermined channel region defined by a barrier layer; (b) forming an oxide layer on said channel region, and then forming a first conducting layer on said oxide layer and said barrier layer, to form a trench on said channel region; (c) applying ion implantation to implant ions of a first conductivity type through said trench into said substrate to form said localized anti-punchthrough region therein by using said first conducting layer as a mask; (d) forming a second conducting layer on said first conducting layer to fill up said trench; (e) removing said barrier layer to form a gate; and (f) applying ion implantation to implant ions of a second conductivity type into said substrate to form source/drain regions.
Claim 2
Independent Claim
151 words
A method of forming a MOS device having a localized anti-punchthrough region, comprising the steps of: (a) providing a silicon substrate doped with impurities of a first conductivity type and having a predetermined channel region defined by a barrier layer; (b) forming an oxide layer on said channel region, and then forming a first conducting layer on said oxide layer and said barrier layer, to form a trench on said channel region; (c) applying ion implantation to implant ions of a first conductivity type through said trench into said substrate to form said localized anti-punchthrough region therein by using said first conducting layer as a mask; (d) forming a second conducting layer on said first conducting layer to fill up said trench; (e) removing said barrier layer to form a gate; and (f) applying ion implantation to implant ions of a second conductivity type into said substrate to form source/drain regions.
Claim 3
Dependent Claim
38 words
The method of claim 1, wherein step (e) further comprises: applying ion implantation to implant ions of a second conductivity type into said substrate to form lightly-doped regions therein; and forming spacers on the sidewall of said gate.
Claim 4
Dependent Claim
33 words
The method of claim 1, further comprising a step, between step (a) and step (b), of applying ion implantation to implant ions of a first conductivity into said substrate through said channel region.
Claim 5
Dependent Claim
38 words
The method of claim 1, further comprising a step, between step (d) and step (e), of planarizing said first conducting layer and said second conducting layer to be in alignment with the top surface of said barrier layer.
Claim 6
Dependent Claim
16 words
The method of claim 4 wherein said planarization step is carried out by chemical mechanical polishing.
Claim 7
Dependent Claim
12 words
The method of claim 1, wherein said barrier layer is silicon oxide.
Claim 8
Dependent Claim
12 words
The method of claim 1, wherein said barrier layer is silicon nitride.
Claim 9
Dependent Claim
14 words
The method of claim 1, wherein said first conducting layer is an impurity-doped polysilicon.
Claim 10
Dependent Claim
12 words
The method of claim 1, wherein said second conducting layer is polysilicon.
Claim 11
Dependent Claim
12 words
The method of claim 1, wherein said second conducting layer is silicide.
Claim 12
Dependent Claim
14 words
The method of claim 1, wherein said second conducting layer is a refractory metal.
Claim 13
Dependent Claim
17 words
The method of claim 1, wherein said first type is P-type and said second type is N-type.
Claim 14
Dependent Claim
17 words
The method of claim 1, wherein said first type is N-type and said second type is P-type.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |