Patent EP0034441A1 successfully refreshed from Google Patents.
Patent US6470489B1 successfully refreshed from Google Patents.
US6470489B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Design rule checking system and method
Assignee: Synopsys Inc
•
Filing: 1998-09-16
•
Granted: 2002-10-22
•
Expires: 2018-09-16
Abstract
Abstract A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.
Inventors
- 👤 Fang-Cheng Chang
- 👤 Yao-Ting Wang
- 👤 Yagyensh C. Pati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:39
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; G06F2119/00; G06F2119/18
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
69 words
A method for performing design rule checking for an integrated circuit layout having been subjected to optical proximity correction OPC so that the integrated circuit layout includes OPC features, comprising: taking said integrated circuit layout including OPC features; generating a simulation of an exposure made using said integrated circuit layout; using said simulation to construct a second layout data; and performing design rule checking of said second layout data.
Claim 2
Independent Claim
69 words
A method for performing design rule checking for an integrated circuit layout having been subjected to optical proximity correction OPC so that the integrated circuit layout includes OPC features, comprising: taking said integrated circuit layout including OPC features; generating a simulation of an exposure made using said integrated circuit layout; using said simulation to construct a second layout data; and performing design rule checking of said second layout data.
Claim 3
Dependent Claim
26 words
The method of claim 1 , wherein said using said simulation includes tracing a contour of features in said simulation to produce said second layout data.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein said second layout data comprises a GDS-II layout data.
Claim 5
Dependent Claim
15 words
The method of claim 1 , wherein said OPC features include at least one serif.
Claim 6
Dependent Claim
28 words
The method of claim 1 , wherein said using said second layout data comprises a machine-readable polygon representation of an intensity contour in an image of said simulation.
Claim 7
Independent Claim
70 words
A method for producing an integrated circuit layout, comprising: subjecting a layout to optical proximity correction OPC to produce an integrated circuit layout including OPC features; generating a simulation of an exposure made using said integrated circuit layout; using said simulation to construct a second layout data; performing design rule checking of said second layout data; and correcting said integrated circuit layout based upon results of said design rule checking.
Claim 8
Independent Claim
70 words
A method for producing an integrated circuit layout, comprising: subjecting a layout to optical proximity correction OPC to produce an integrated circuit layout including OPC features; generating a simulation of an exposure made using said integrated circuit layout; using said simulation to construct a second layout data; performing design rule checking of said second layout data; and correcting said integrated circuit layout based upon results of said design rule checking.
Claim 9
Dependent Claim
25 words
The method of claim 6 , wherein said using said simulation tracing a contour of features in said simulation to produce said second layout data.
Claim 10
Dependent Claim
16 words
The method of claim 6 , wherein said second layout data comprises a GDS-II layout data.
Claim 11
Dependent Claim
15 words
The method of claim 6 , wherein said OPC features include at least one serif.
Claim 12
Dependent Claim
28 words
The method of claim 6 , wherein said using said second layout data comprises a machine-readable polygon representation of an intensity contour in an image of said simulation.
Claim 13
Dependent Claim
23 words
The method of claim 6 , wherein said generating, using and correcting are performed iteratively until the corrected layout is within predetermined tolerance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |