Mask for optical lithography using phase shift masking and integrated circuit produced therefrom

Claim 2

An integrated circuit being formed from a mask which is manufactured by the process of: providing a mask substrate; forming a gate level pattern on the mask substrate; identifying regions of the mask substrate which correspond to active regions of the integrated circuit and identifying one or more portions of the gate level pattern which overlap with the active regions of the integrated circuit; and forming phase shift regions of different phases on opposite sides of at least one identified portion so as to cause light transmitted through the opposite sides to destructively interfere with each other.

Claim 3

An integrated circuit as recited in claim 1, wherein the step of forming includes etching a portion of the mask substrate to alter the phase of the light transmitted therethrough by 180°.

Claim 4

An integrated circuit as recited in claim 1, wherein the step of forming includes depositing an additional layer of the mask substrate to alter the phase of the light transmitted therethrough by 180°.

Claim 5

An integrated circuit as recited in claim 1, wherein the step of forming includes forming phase shift regions of opposite phases on the opposite sides.

Claim 6

An integrated circuit as recited in claim 1, wherein the step of forming includes forming phase shift regions having phases differing by 180° on the opposite sides.

Claim 7

An integrated circuit as recited in claim 5, wherein the step of forming includes maintaining a phase of x° on one side of said at least one identified portion and altering a phase on an opposite side of said at least one identified portion to be x+180°.

Claim 8

An integrated circuit as recited in claim 6, wherein the process of forming the mask further comprises the steps of: identifying regions, other than said one or more identified portions, which cause light transmitted through opposite sides thereof to destructively interfere with each other; and forming a transition phase shift region adjacent to each of the identified regions, the transition phase shift region including two or more additional phase shift regions.

Claim 9

An integrated circuit as recited in claim 1, wherein the process of forming the mask further comprises the steps of: comparing widths of the identified portions with a minimum width; and maintaining an equal-valued phase shift on both sides of the identified portions whose widths are larger than the minimum width.

Claim 10

An integrated circuit as recited in claim 8, wherein the step of forming includes the steps of: for each identified region corresponding to the active regions of the integrated circuit and intersected by the gate level pattern, determining a contiguous piece of the identified region; and if the contiguous piece of the identified region has a length greater than 2W i +W c , dividing the contiguous piece into two separate phase shift regions with a separation distance of at least W c .

Claim 11

An integrated circuit as recited in claim 9, wherein the step of forming further includes the steps of: determining distances between each pair of identified portions; and if any of the distances is less than 2W i +W c , maintaining one continuous phase shift region between any such pair of identified portions.

Claim 12

An integrated circuit as recited in claim 10, further comprising the step of verifying that a phase shift difference of the phase shift regions on either side of each identified portion whose width is less than or equal to the minimum width is 180°.

Claim 13

An integrated circuit (IC) being formed from an i-line stepper lithography method for phase shift mask patterning for forming the levels of the IC on a semiconductor wafer, said lithography method including use of different masks to pattern the layout of different levels, one such level being the gate level and a second such level being the active regions, said active regions being spatially defined by an active region layout pattern, said gate level being spatially defined by a gate level pattern having first and second gate level layout portions, said first gate level layout portion being a standard non-phase shift mask pattern having opaque and non-opaque regions and said second gate level layout portion having areas containing phase shift regions, wherein said method comprises: performing a comparative analysis of said active region layout pattern and said gate level layout portion to spatially establish Intersection regions corresponding to the regions on the IC where said active region layout pattern and said first gate level layout portion overlay, said Intersection regions being rectangles having a pair of parallel long sides and a pair of parallel short sides; constructing a transmissive light field phase shift mask (PSM) having various phase shifted regions and opaque regions for patterning said gate level, said PSM comprising said gate level layout pattern, said gate level layout pattern being identical to said first gate level layout portion except in the regions on said PSM corresponding to said Intersection regions, said gate level layout pattern including zero degree phase shift regions which are contiguous with one of said parallel long sides of said regions corresponding to Intersection regions and a 180 degree phase shift region contiguous with the other of said parallel long sides of said regions corresponding to said Intersection regions, said opaque pattern of said transmissive light field PSM corresponding to said Intersection regions and to said opaque regions of said first gate level layout portion; and aligning said PSM in said i-line stepper and exposing a positive resist on said wafer with a light source directed through said transmissive light field PSM by focusing with a lens system of said i-line stepper said light which transmits through said PSM onto said positive resist on said wafer.

Claim 14

An integrated circuit (IC) being formed from an i-line stepper lithography method for phase shift mask patterning for forming the levels of the IC on a semiconductor wafer, said lithography method including use of different masks to pattern the layout of different levels, one such level being the gate level and a second such level being the active regions, said active regions being spatially defined by an active region layout pattern, said gate level being spatially defined by a gate level pattern having first and second gate level layout portions, said first gate level layout portion being a standard non-phase shift mask pattern having opaque and non-opaque regions and said second gate level layout portion having areas containing phase shift regions, wherein said method comprises: performing a comparative analysis of said active region layout pattern and said gate level layout portion to spatially establish Intersection regions corresponding to the regions on the IC where said active region layout pattern and said first gate level layout portion overlay, said Intersection regions being rectangles having a pair of parallel long sides and a pair of parallel short sides; constructing a transmissive light field phase shift mask (PSM) having various phase shifted regions and opaque regions for patterning said gate level, said PSM comprising said gate level layout pattern, said gate level layout pattern being identical to said first gate level layout portion except in the regions on said PSM corresponding to said Intersection regions, said gate level layout pattern including zero degree phase shift regions which are contiguous with one of said parallel long sides of said regions corresponding to Intersection regions and a 180 degree phase shift region contiguous with the other of said parallel long sides of said regions corresponding to said Intersection regions, said opaque pattern of said transmissive light field PSM corresponding to said Intersection regions and to said opaque regions of said first gate level layout portion; and aligning said PSM in said i-line stepper and exposing a positive resist on said wafer with a light source directed through said transmissive light field PSM by focusing with a lens system of said i-line stepper said light which transmits through said PSM onto said positive resist on said wafer.

Claim 15

An integrated circuit as recited in claim 12, wherein said method further comprises the steps of: providing on said phase shift mask a compensating transition phase shift region around and contiguous to said 180 degree phase shift regions and between said 180 degree phase shift regions and said zero phase regions, said compensating transition phase shift region being contiguous with the entire periphery of said 180 degree phase area except for the region where said 180 degree phase area overlaps a region having said opaque pattern thereon.

Claim 16

An integrated circuit as recited in claim 13, wherein said compensating transition phase shift region comprises a first region of 60 degrees shift and a second region of 120 degrees shift where said 120 degree region is intermediate between said sixty degree region and said 180 degree region.

Claim 17

An integrated circuit as recited in claim 13, wherein said gate level layout pattern includes a first area having a first gate length and a second area having a second gate length, wherein said first gate length area is shorter than said second gate length area, and wherein said first gate length is the width of said Intersection regions covered by said first area.

Claim 18

An integrated circuit as recited in claim 13, wherein said compensating transition phase region includes a linearly graded transition.

Claim 19

An integrated circuit as recited in claim 13, wherein said 180 degree phase shift regions are layered regions of said PSM providing a lagging phase of said light which transmits through said 180 degree phase shift region relative to the phase of said light which does not pass through said 180° phase shift region.

Claim 20

An integrated circuit as recited in claim 13, wherein said 180 degree phase shift regions are etched regions of said PSM providing a leading phase of said light which transmits through said 180 degree phase shift region relative to the phase of said light which does not pass through said 180° phase shift region.

Claim 21

An integrated circuit as recited in claim 18, wherein said method further comprises the steps of: constructing a trim mask having a dark field surrounding a transmission pattern, said transmission pattern being a pattern having a center line which exactly corresponds to the locus of some of the transitions between zero degree to 180 degree regions; before the step of developing said exposed positive resist, again exposing said positive resist on said integrated circuit with a partially coherent light source directed through said trim mask which trim mask has been aligned so that the zero to 180 degree locus of said trim mask is aligned with said 0°/180° transitions regions exposed during said first exposure; and developing said resist layer.

Claim 22

An integrated circuit as recited in claim 13, wherein the step of providing on said phase shift mask a compensation transition phase shift region around and contiguous to said 180 degree phase shift regions includes the step of determining a physical distance between adjoining 180 degree phase shift regions and combining adjoining 180 degree phase shift regions together if said physical distance is less than the minimum distance required to provide said transition phase shift region around each said 180 degree phase shift region.

Claim 23

An integrated circuit as recited in claim 12, wherein said method further comprises the steps of: constructing a trim mask having a transmission pattern for passing light from said light source, said trim mask having a dark field completely surrounding said transmission pattern, said transmission pattern being a pattern having lines of width T having a center line, where the locus of said center line exactly corresponds to the locus of all edges where 0 degree regions abut to 180 degree regions on said gate level layout pattern and where T is greater than the natural line width of the stepper; after said step of exposing but before the step of developing said exposed positive resist layer, replacing said PSM with said trim mask and exposing again said positive resist layer on said IC with said partially coherent light source directed through said trim mask wherein said trim mask has been aligned so that said center edges said transmission patterns of said trim mask are aligned with said locus of the line of where 0 degree and 180 degree regions abutted during said first exposure; and developing said resist layer.

Claim 24

An integrated circuit as recited in claim 12, wherein the method further comprises the steps of: constructing a trim mask having a dark field surrounding a transmission pattern, said transmission pattern being a pattern having a center line which exactly corresponds to the locus of some of transitions between a zero degree to 180 degree regions; before the step of developing said exposed positive resist, again exposing said positive resist on said integrated circuit with a partially coherent light source directed through said trim mask which trim mask has been aligned so that the zero to 180 degree locus of said trim mask is aligned with said 0°/180° transitions regions exposed during said first exposure; and developing said resist layer.

Claim 25

A mask for producing a gate level pattern on a substrate of an integrated circuit, comprising: a light-transmissive mask substrate; an opaque gate level pattern formed on the mask substrate; phase shift regions of different phases formed on opposite sides of those portions of the opaque gate level pattern which overlap with active regions of the integrated circuit, but not on opposite sides of those portions of the opaque gate level pattern which do not overlap with active regions of the integrated circuit.

Claim 26

A mask for producing a gate level pattern on a substrate of an integrated circuit, comprising: a light-transmissive mask substrate; an opaque gate level pattern formed on the mask substrate; phase shift regions of different phases formed on opposite sides of those portions of the opaque gate level pattern which overlap with active regions of the integrated circuit, but not on opposite sides of those portions of the opaque gate level pattern which do not overlap with active regions of the integrated circuit.

Claim 27

A mask as recited in claim 23, wherein some phase shift regions include etched portions which alter the phase of the light transmitted therethrough by 180°.

Claim 28

A mask as recited in claim 23, wherein some phase shift regions include thicker portions which alter the phase of the light transmitted therethrough by 180°.

Claim 29

A mask as recited in claim 23, wherein the phase shift regions on opposite sides of the overlapping portions are out of phase with each other by 180°.

Claim 30

A mask as recited in claim 26, one side of the overlapping portions has a phase of x° and the opposite side of the overlapping portions has a phase of x+180°.

Claim 31

A mask as recited in claim 27, further comprising transition phase shift regions formed adjacent to regions, other than the overlapping portions, which cause light transmitted through opposite sides thereof to destructively interfere with each other, the transition phase shift region including two or more additional phase regions.

Claim 32

A mask as recited in claim 28, wherein the phases of the additional phase regions increase linearly.

Claim 33

A mask as recited in claim 28, wherein the phases of the additional phase regions increase stepwise.

Claim 34

A mask as recited in claim 23, wherein the identified portions whose widths are larger than a minimum width have phase shift regions with a phase of x° on either side thereof.