US6081658A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Proximity correction system for wafer lithography
Assignee: Synopsys Inc
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Filing: 1997-12-31
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Granted: 2000-06-27
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Expires: 2017-12-31
Abstract
Abstract A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0. Another method for computing a two-dimensional convolution value for any point (x,y) on a polygonal pattern includes the steps of identifying a set of half-plane basis functions corresponding to each face angle of the polygonal pattern, convolving each half-plane basis function with a convolution kernel using integration to find convolved flash (cflash) x,y values, storing the cflash (x,y) values to a two-dimensional look-up table, decomposing the polygonal pattern into a set of flashes where each of the flashes is an instance of the half-plane basis functions, and computing a convolution value for point (x,y) by looking-up a corresponding cflash x,y value for each flash in the table and summing together the corresponding cflash x,y values. The present invention may be used in a method for determining correction steps to which a design layout is to be subjected during wafer proximity correction.
Inventors
- 👤 Michael L. Rieger
- 👤 John P. Stirniman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:03
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G03F7/70441
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
104 words
A method for performing proximity correction on design layouts, said method for correction comprising the steps of: (a) forming a process model using one or more convolution kernels to simulate wafer image distribution; (b) convolving an original design layout with said convolution kernels to obtain a simulated wafer image; (c) iteratively adjusting shapes of said original design layout until said simulated wafer image coincides with said original design layout to produce proximity corrected output; (d) creating a corrected mask using said proximity corrected output; and (e) using said corrected mask, subjecting a wafer to lithography and wafer processes to produce a corrected production wafer.
Claim 2
Independent Claim
104 words
A method for performing proximity correction on design layouts, said method for correction comprising the steps of: (a) forming a process model using one or more convolution kernels to simulate wafer image distribution; (b) convolving an original design layout with said convolution kernels to obtain a simulated wafer image; (c) iteratively adjusting shapes of said original design layout until said simulated wafer image coincides with said original design layout to produce proximity corrected output; (d) creating a corrected mask using said proximity corrected output; and (e) using said corrected mask, subjecting a wafer to lithography and wafer processes to produce a corrected production wafer.
Claim 3
Independent Claim
121 words
A method for determining correction steps to which a design layout is to be subjected during wafer proximity correction, said method for determining comprising the steps of: (a) subjecting a characterizing pattern to lithography and wafer processes to produce an uncorrected test wafer; (b) forming a proximity behavior model using measurements of critical dimensions of said uncorrected test wafer; (c) forming a correction recipe from said proximity behavior model; (d) subjecting a new IC layout design to proximity correction to produce proximity corrected output, said proximity correction using said recipe library; (e) creating a corrected mask using said proximity corrected output; and (f) using said corrected mask, subjecting a wafer to lithography and wafer processes to produce a corrected production wafer.
Claim 4
Independent Claim
121 words
A method for determining correction steps to which a design layout is to be subjected during wafer proximity correction, said method for determining comprising the steps of: (a) subjecting a characterizing pattern to lithography and wafer processes to produce an uncorrected test wafer; (b) forming a proximity behavior model using measurements of critical dimensions of said uncorrected test wafer; (c) forming a correction recipe from said proximity behavior model; (d) subjecting a new IC layout design to proximity correction to produce proximity corrected output, said proximity correction using said recipe library; (e) creating a corrected mask using said proximity corrected output; and (f) using said corrected mask, subjecting a wafer to lithography and wafer processes to produce a corrected production wafer.
Claim 5
Dependent Claim
95 words
Method for computing a pattern function for a polygonal pattern, said polygonal pattern having a finite number of predetermined face angles, said method comprising the steps of: (a) identifying a set of half-plane basis functions corresponding to each of said face angles; (b) decomposing the polygon into a set of flashes where each flash is an instance of a half-plane basis function; and (c) computing said pattern function by summing together all flashes evaluated at a point (x,y), said pattern function returning a 1 if (x,y) is inside a polygon and otherwise returning a 0.
Claim 6
Dependent Claim
95 words
Method for computing a pattern function for a polygonal pattern, said polygonal pattern having a finite number of predetermined face angles, said method comprising the steps of: (a) identifying a set of half-plane basis functions corresponding to each of said face angles; (b) decomposing the polygon into a set of flashes where each flash is an instance of a half-plane basis function; and (c) computing said pattern function by summing together all flashes evaluated at a point (x,y), said pattern function returning a 1 if (x,y) is inside a polygon and otherwise returning a 0.
Claim 7
Independent Claim
131 words
A method for computing a two-dimensional convolution value for any point x,y on a polygonal pattern, said polygonal pattern having a finite number of face angles, said method comprising the steps of: (a) identifying a set of half-plane basis functions corresponding to each of said face angles; (b) convolving said half-plane basis functions with a convolution kernel using integration to find flash x,y values; (c) saving said convolved flash x,y values to a two-dimensional look-up table; (d) decomposing said polygonal pattern into a set of flashes where each of said flashes is an instance of said half-plane basis functions; (e) for point x,y, computing a convolution value by looking up a corresponding convolved flash x,y value for each flash in the table and summing together said corresponding convolved flash x,y values.
Claim 8
Independent Claim
131 words
A method for computing a two-dimensional convolution value for any point x,y on a polygonal pattern, said polygonal pattern having a finite number of face angles, said method comprising the steps of: (a) identifying a set of half-plane basis functions corresponding to each of said face angles; (b) convolving said half-plane basis functions with a convolution kernel using integration to find flash x,y values; (c) saving said convolved flash x,y values to a two-dimensional look-up table; (d) decomposing said polygonal pattern into a set of flashes where each of said flashes is an instance of said half-plane basis functions; (e) for point x,y, computing a convolution value by looking up a corresponding convolved flash x,y value for each flash in the table and summing together said corresponding convolved flash x,y values.
References Cited (Backward Citations)
US4812962A
Cited
US5182718A
Cited
US5051598A
Cited
US5241185A
Cited
US5242770A
Cited
US5340700A
Cited
US5256505A
Cited
US5432714A
Cited
US5533148A
Cited
US5424154A
Cited
US5447810A
Cited
US5532090A
Cited
US5825647A
Cited
US5553273A
Cited
US5657235A
Cited
US5863682A
Cited
US5847959A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |