Patent US6370679B1 successfully refreshed from Google Patents.
US6370679B1
Expired / Lapsed
US
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Data hierarchy layout correction and verification method and apparatus
Assignee: Synopsys Inc
•
Filing: 1998-09-16
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Granted: 2002-04-09
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Expires: 2018-09-16
Abstract
Abstract A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.
Inventors
- 👤 Fang-Cheng Chang
- 👤 Yao-Ting Wang
- 👤 Yagyensh C. Pati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:53
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36
Claims Analysis
Total Claims: 107
Claim 1
Independent Claim
192 words
A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising: providing the integrated circuit layout design as a first input; providing a particular set of correction criteria as a second input; analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria; generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises: generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 2
Independent Claim
192 words
A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising: providing the integrated circuit layout design as a first input; providing a particular set of correction criteria as a second input; analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria; generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises: generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 3
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the first program data is provided on a computer readable media.
Claim 4
Dependent Claim
24 words
The method of generating proximity corrections for an integrated circuit layout of claim 2 wherein the computer readable media comprises a hard disk drive.
Claim 5
Dependent Claim
22 words
The method of generating proximity corrections for an integrated circuit layout of claim 2 wherein the computer readable media comprises a server.
Claim 6
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 7
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 5 wherein the first program data is described by a GDS-II data file.
Claim 8
Dependent Claim
30 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.
Claim 9
Dependent Claim
28 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.
Claim 10
Dependent Claim
32 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the particular set of correction criteria comprises a criteria for specifically identifying transistor gates in the layout.
Claim 11
Dependent Claim
32 words
The method of generating proximity corrections for an integrated circuit layout of claim 9 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.
Claim 12
Dependent Claim
41 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 further comprising combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.
Claim 13
Dependent Claim
39 words
The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.
Claim 14
Dependent Claim
45 words
The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 15
Dependent Claim
88 words
The method of generating proximity corrections for an integrated circuit layout of claim 11 further comprising: providing a set of layout accuracy parameters; comparing the first corrected layout to the design accuracy parameters; providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 16
Dependent Claim
50 words
The method of generating proximity corrections for an integrated circuit layout of claim 14 further comprising: providing the second corrected layout to a design rule checker; operating the design rule checker; and determining whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 17
Dependent Claim
78 words
The method of generating proximity corrections for an integrated circuit layout of claim 14 , wherein comparing the first corrected layout to the design accuracy parameters further comprises: providing the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce; providing the actual image of the exposure that was designed for the integrated circuit; and measuring the difference between the simulated image and the actual image.
Claim 18
Dependent Claim
28 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.
Claim 19
Dependent Claim
48 words
The method of generating proximity corrections for an integrated circuit layout of claim 1 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 20
Dependent Claim
210 words
A program storage device readable by a machine storing a program of instructions executable by the machine to perform method steps for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising: providing the integrated circuit layout as a first input; providing a particular set of correction criteria as a second input; analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria; generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction rules; and providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises: generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 21
Dependent Claim
210 words
A program storage device readable by a machine storing a program of instructions executable by the machine to perform method steps for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the method comprising: providing the integrated circuit layout as a first input; providing a particular set of correction criteria as a second input; analyzing the integrated circuit layout to identify features of the layout that meet the particular set of correction criteria; generating proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction rules; and providing a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein providing the first program data comprises: generating a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 22
Dependent Claim
19 words
The program storage device of claim 19 wherein the first program data is provided on a computer readable media.
Claim 23
Dependent Claim
17 words
The program storage device of claim 20 wherein the computer readable media comprises a hard disk drive.
Claim 24
Dependent Claim
15 words
The program storage device of claim 20 wherein the computer readable media comprises a server.
Claim 25
Dependent Claim
19 words
The program storage device of claim 19 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 26
Dependent Claim
19 words
The program storage device of claim 23 wherein the first program data is described by a GDS-II data file.
Claim 27
Dependent Claim
23 words
The program storage device of claim 19 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.
Claim 28
Dependent Claim
21 words
The program storage device of claim 19 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.
Claim 29
Dependent Claim
25 words
The program storage device of claim 19 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.
Claim 30
Dependent Claim
25 words
The program storage device of claim 27 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.
Claim 31
Dependent Claim
37 words
The program storage device of claim 19 , the method further comprising combining the first program data with the data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.
Claim 32
Dependent Claim
35 words
The program storage device of claim 29 , the method further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.
Claim 33
Dependent Claim
41 words
The program storage device of claim 29 , the method further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 34
Dependent Claim
84 words
The program storage device of claim 29 , the method further comprising: providing a set of layout accuracy parameters; comparing the first corrected layout to the design accuracy parameters; providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 35
Dependent Claim
46 words
The program storage device of claim 32 , the method further comprising: providing the second corrected layout to a design rule checker; operating the design rule checker; and determining whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 36
Dependent Claim
71 words
The program storage device of claim 32 , wherein comparing the first corrected layout to the design accuracy parameters further comprises: providing the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce; providing the actual image of the exposure that was designed for the integrated circuit; and measuring the difference between the simulated image and the actual image.
Claim 37
Dependent Claim
21 words
The program storage device of claim 19 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.
Claim 38
Dependent Claim
41 words
The program storage device of claim 19 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 39
Independent Claim
200 words
An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the apparatus comprising: a first input that receives the integrated circuit layout; a second input that receives a particular set of correction criteria; a resource that analyzes the integrated circuit layout and identifies features that meet the particular set of correction criteria; a resource that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and a resource that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the resource for providing the first program data further: generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 40
Independent Claim
200 words
An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the apparatus comprising: a first input that receives the integrated circuit layout; a second input that receives a particular set of correction criteria; a resource that analyzes the integrated circuit layout and identifies features that meet the particular set of correction criteria; a resource that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and a resource that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the resource for providing the first program data further: generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 41
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the first program data is provided on a computer readable media.
Claim 42
Dependent Claim
24 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 38 wherein the computer readable media comprises a hard disk drive.
Claim 43
Dependent Claim
22 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 38 wherein the computer readable media comprises a server.
Claim 44
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 45
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 41 wherein the first program data is described by a GDS-II data file.
Claim 46
Dependent Claim
30 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.
Claim 47
Dependent Claim
28 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.
Claim 48
Dependent Claim
32 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.
Claim 49
Dependent Claim
32 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 45 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.
Claim 50
Dependent Claim
44 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 further comprising a resource that combines the first program data with the data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.
Claim 51
Dependent Claim
46 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising a resource that flattens the second program data to produce a third program data, and a resource that utilizes the third program data to produce an optically corrected lithographic mask.
Claim 52
Dependent Claim
45 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising a design rule checker that receives the second program data and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 53
Dependent Claim
101 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 47 further comprising: a third input that receives a set of layout accuracy parameters; a resource that compares the first corrected layout to the design accuracy parameters; a resource that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and a resource that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 54
Dependent Claim
45 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 50 further comprising a design rule checker that receives the second corrected mask and determines whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 55
Dependent Claim
87 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 50 , wherein comparing the first corrected layout to the design accuracy parameters further comprises: a resource that provides the second program data to a checker device which produces a simulated image of the exposure that the first corrected layout would produce; a resource that provides the actual image of the exposure that was designed for the integrated circuit; and a resource that measures the difference between the simulated image and the actual image.
Claim 56
Dependent Claim
28 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the integrated circuit layout comprises a plurality of cells in a tree structure.
Claim 57
Dependent Claim
48 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 37 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 58
Dependent Claim
248 words
A computer program product, comprising: a computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the computer readable program code comprising: computer readable program code that reads the integrated circuit layout as a first input; computer readable program code that reads a particular set of correction criteria as a second input; computer readable program code that analyzes the integrated circuit layout to identify features that meet the particular set of correction criteria; computer readable program code that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and computer readable program code that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the computer readable program code that provides a first program data computer further comprises: computer readable program code that generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 59
Dependent Claim
248 words
A computer program product, comprising: a computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical structure including a plurality of layout cells, the computer readable program code comprising: computer readable program code that reads the integrated circuit layout as a first input; computer readable program code that reads a particular set of correction criteria as a second input; computer readable program code that analyzes the integrated circuit layout to identify features that meet the particular set of correction criteria; computer readable program code that generates proximity correction data in response to the particular set of correction criteria for the features that meet the particular set of correction criteria; and computer readable program code that provides a first program data wherein the first program data comprises the proximity correction data configured in a hierarchical structure that substantially preserves the plurality of layout cells in the hierarchical structure of the integrated circuit layout, wherein the computer readable program code that provides a first program data computer further comprises: computer readable program code that generates a plurality of delta planes corresponding to the plurality of cells wherein each delta plane comprises data representative of the difference between a correction plane of the cell corresponding to the delta plane and the delta planes corresponding to the children cells of the cell corresponding to the delta plane.
Claim 60
Dependent Claim
40 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the first program data is provided on a computer readable media.
Claim 61
Dependent Claim
38 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 56 wherein the computer readable media comprises a hard disk drive.
Claim 62
Dependent Claim
36 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 56 wherein the computer readable media comprises a server.
Claim 63
Dependent Claim
40 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 64
Dependent Claim
40 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 59 wherein the first program data is described by a GDS-II data file.
Claim 65
Dependent Claim
44 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the proximity correction data comprises data corresponding to the addition of serifs to the layout.
Claim 66
Dependent Claim
42 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the proximity correction data comprises data corresponding to the correction of transistor gates.
Claim 67
Dependent Claim
46 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.
Claim 68
Dependent Claim
46 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 63 wherein the proximity correction data comprises data corresponding to the addition of hammerhead features to transistor line ends.
Claim 69
Dependent Claim
59 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 further comprising computer readable program code that combines the first program data with data describing the integrated circuit mask to produce a second program data that describes a first corrected layout.
Claim 70
Dependent Claim
65 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising a computer readable program code that flattens the second program data to produce a third program data, and a computer readable program code that utilizes the third program data to produce a corrected lithographic mask.
Claim 71
Dependent Claim
64 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising a computer readable program code that receives the second program data as a third input and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 72
Dependent Claim
130 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 65 further comprising: a computer readable program code that receives a set of layout accuracy parameters as a third input; a computer readable program code that compares the first corrected layout to the design accuracy parameters; a computer readable program code that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and a computer readable program code that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 73
Dependent Claim
64 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 68 further comprising a computer readable program code that receives the second corrected mask as a fourth input and determines whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 74
Dependent Claim
109 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 68 , wherein the computer readable program code that compares the corrected layout to the design accuracy parameters further comprises: a computer readable program code that receives the second program and produces a simulated image of the exposure that the corrected layout would produce; a computer readable program code that provides the actual image of the exposure that was designed for the integrated circuit; and a computer readable program code that measures the difference between the simulated image and the actual image.
Claim 75
Dependent Claim
62 words
The computer usable medium having a computer readable program code embodied therein for causing a computer to generate proximity corrections for an integrated circuit layout of claim 55 wherein the correction plane for each cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 76
Independent Claim
174 words
A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the method comprising: providing the integrated circuit layout as a first input; providing a particular set of correction criteria as a second input; compiling the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the hierarchical tree structure in response to the particular set of correction criteria; linking the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell's child cells and interaction between the cell's primitive geometry and each of the cell's child cells; and providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.
Claim 77
Independent Claim
174 words
A method of generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the method comprising: providing the integrated circuit layout as a first input; providing a particular set of correction criteria as a second input; compiling the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the hierarchical tree structure in response to the particular set of correction criteria; linking the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell's child cells and interaction between the cell's primitive geometry and each of the cell's child cells; and providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.
Claim 78
Dependent Claim
82 words
The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein for each cell in the hierarchical tree structure the sum of the delta plane of the cell and the delta planes of the cell's child cells comprises a correction plane of the cell wherein the correction plane for the cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 79
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the first program data is provided on a computer readable media.
Claim 80
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 81
Dependent Claim
26 words
The method of generating proximity corrections for an integrated circuit layout of claim 75 wherein the first program data is described by a GDS-II data file.
Claim 82
Dependent Claim
32 words
The method of generating proximity corrections for an integrated circuit layout of claim 72 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.
Claim 83
Dependent Claim
41 words
The method of generating proximity corrections for an integrated circuit layout of claim 72 further comprising combining the first program data with the data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.
Claim 84
Dependent Claim
39 words
The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.
Claim 85
Dependent Claim
45 words
The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 86
Dependent Claim
88 words
The method of generating proximity corrections for an integrated circuit layout of claim 78 further comprising: providing a set of layout accuracy parameters; comparing the first corrected layout to the design accuracy parameters; providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 87
Dependent Claim
45 words
The method of generating proximity corrections for an integrated circuit layout of claim 81 further comprising providing the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 88
Independent Claim
182 words
An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the apparatus comprising: a first input that receives the integrated circuit layout; a second input that receives a particular set of correction criteria; a resource that compiles the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the tree structure in response to the particular set of correction criteria; a resource that links the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell's child cells and interaction between the cell's primitive geometry and each of the cell's child cells; and a resource that provides a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.
Claim 89
Independent Claim
182 words
An apparatus for generating proximity corrections for an integrated circuit layout, wherein the data describing the integrated circuit layout comprises a hierarchical tree structure comprising a plurality of cells, the apparatus comprising: a first input that receives the integrated circuit layout; a second input that receives a particular set of correction criteria; a resource that compiles the hierarchical tree structure, wherein compiling comprises generating a first correction layer for each cell of the plurality of cells in the tree structure in response to the particular set of correction criteria; a resource that links the hierarchical tree structure, wherein linking comprises modifying the correction layer of each cell to generate a delta plane for each cell such that the delta plane of each cell accounts for interaction between each of the cell's child cells and interaction between the cell's primitive geometry and each of the cell's child cells; and a resource that provides a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical tree structure of the integrated circuit layout.
Claim 90
Dependent Claim
82 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein for each cell in the hierarchical tree structure the sum of the delta plane of the cell and the delta planes of the cell's child cells comprises a correction plane of the cell wherein the correction plane for the cell comprises data that would generate an output data equal to a corrected design for the cell if the correction plane were applied to the flattened cell data.
Claim 91
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the first program data is provided on a computer readable media.
Claim 92
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the integrated circuit layout is described by a GDS-II data file.
Claim 93
Dependent Claim
26 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 86 wherein the first program data is described by a GDS-II data file.
Claim 94
Dependent Claim
32 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 wherein the particular set of correction criteria comprises a means for specifically identifying transistor gates in the layout.
Claim 95
Dependent Claim
43 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 83 further comprising a resource that combines the first program data with data describing the integrated circuit layout to produce a second program data that describes a first corrected layout.
Claim 96
Dependent Claim
46 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising a resource that flattens the second program data to produce a third program data, and a resource that utilizes the third program data to produce an optically corrected lithographic mask.
Claim 97
Dependent Claim
45 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising a design rule checker that receives the second program data and determines whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 98
Dependent Claim
101 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 89 further comprising: a third input that receives a set of layout accuracy parameters; a resource that compares the first corrected layout to the design accuracy parameters; a resource that provides a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and a resource that applies the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 99
Dependent Claim
48 words
The apparatus for generating proximity corrections for an integrated circuit layout of claim 92 further comprising a resource that provides the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 100
Independent Claim
197 words
A method for laying out a layer in an integrated circuit, comprising: defining a layout using a hierarchical structure including a plurality of layout cells combined according to the hierarchical structure to generate said layout; traversing the plurality of layout cells in the hierarchical structure to compile correction data for the layout, the correction data defining changes in the layout; and linking the correction data to the hierarchical structure, while substantially preserving the plurality of layout cells in the hierarchical structure, wherein the layout cells include at least one of a primitive geometry and references to child cells in the plurality of layout cells, wherein said correction data comprises delta planes for respective cells in the plurality of layout cells, such that the delta plane of a particular cell in the plurality of layout cells defines changes to correct for interaction between the child cells identified by references in the particular cell, and for interaction between the primitive geometry in the particular cell and said referenced child cells; and providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical structure of the layout.
Claim 101
Independent Claim
197 words
A method for laying out a layer in an integrated circuit, comprising: defining a layout using a hierarchical structure including a plurality of layout cells combined according to the hierarchical structure to generate said layout; traversing the plurality of layout cells in the hierarchical structure to compile correction data for the layout, the correction data defining changes in the layout; and linking the correction data to the hierarchical structure, while substantially preserving the plurality of layout cells in the hierarchical structure, wherein the layout cells include at least one of a primitive geometry and references to child cells in the plurality of layout cells, wherein said correction data comprises delta planes for respective cells in the plurality of layout cells, such that the delta plane of a particular cell in the plurality of layout cells defines changes to correct for interaction between the child cells identified by references in the particular cell, and for interaction between the primitive geometry in the particular cell and said referenced child cells; and providing a first program data comprising the delta planes, wherein the first program data is configured hierarchically such that it corresponds to the hierarchical structure of the layout.
Claim 102
Dependent Claim
34 words
The method of claim 94 , wherein said traversing includes analyzing the plurality of layout cells to identify features of the layout suitable for proximity correction, and generating proximity correction data for such features.
Claim 103
Dependent Claim
35 words
The method of claim 94 , further comprising combining the first program data with the plurality of layout cells in the hierarchical structure to produce a second program data that describes a first corrected layout.
Claim 104
Dependent Claim
31 words
The method of claim 96 , further comprising flattening the second program data to produce a third program data, and utilizing the third program data to produce a corrected lithographic mask.
Claim 105
Dependent Claim
37 words
The method of claim 96 , further comprising providing the second program data to a design rule checker to determine whether the first corrected layout falls within a set of design rules associated with the integrated circuit.
Claim 106
Dependent Claim
80 words
The method of claim 96 , further comprising: providing a set of layout accuracy parameters; comparing the first corrected layout to the design accuracy parameters; providing a model based correction means for correcting all areas of the layout in accordance with a particular set of design accuracy rules; and applying the model based correction means to the first corrected layout to produce a second corrected layout such that the second corrected layout falls within the set of layout accuracy parameters.
Claim 107
Dependent Claim
37 words
The method of claim 99 , further comprising providing the second corrected layout to a design rule checker to determine whether the second corrected layout falls within a set of design rules associated with the integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-08 | 2005-10-08 | 2006-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-08 | 2009-10-08 | 2010-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-08 | 2013-10-08 | 2014-04-09 | $7700.00 | Window Closed / Lapsed |