Patent US6326696B1 successfully refreshed from Google Patents.
US6326696B1
Expired / Lapsed
US
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Electronic package with interconnected chips
Assignee: Cavium International
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Filing: 1998-02-04
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Granted: 2001-12-04
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Expires: 2018-02-04
Abstract
Abstract An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.
Inventors
- 👤 Raymond Robert Horton
- 👤 Alphonso Philip Lanzetta
- 👤 Joseph Maryan Milewski
- 👤 Lawrence S. Mok
- 👤 Robert Kevin Montoye
- 👤 Hussain Shaukatulla
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:53
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W90/00; H10W90/401; H10W90/701; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/90; H10W72/951; H10W72/952; H10W74/00; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
147 words
An electronic package, comprising: a circuitized substrate having a first cavity therein said cavity passing completely through said substrate, and including a first surface and a second surface; a thick planar heatsink having a second cavity, said heatsink bonded to said second surface of said substrate with said second cavity overlapping at least partially said first cavity; a plurality of electrically conductive members positioned on said first surface of said circuitized substrate, at least some of said conductive members located about the periphery of said first cavity; a first semiconductor chip positioned within said first and second cavities and directly electrically connected to said at least some of said conductive members and thermally coupled to said planar heatsink; and a second semiconductor chip positioned on said first semiconductor chip and electrically coupled thereto and having an outer surface substantially coplanar with said first surface of said substrate.
Claim 2
Dependent Claim
147 words
An electronic package, comprising: a circuitized substrate having a first cavity therein said cavity passing completely through said substrate, and including a first surface and a second surface; a thick planar heatsink having a second cavity, said heatsink bonded to said second surface of said substrate with said second cavity overlapping at least partially said first cavity; a plurality of electrically conductive members positioned on said first surface of said circuitized substrate, at least some of said conductive members located about the periphery of said first cavity; a first semiconductor chip positioned within said first and second cavities and directly electrically connected to said at least some of said conductive members and thermally coupled to said planar heatsink; and a second semiconductor chip positioned on said first semiconductor chip and electrically coupled thereto and having an outer surface substantially coplanar with said first surface of said substrate.
Claim 3
Dependent Claim
31 words
The electronic package of claim 1 further including a plurality of electrically conductive wires, said wires electrically coupling said first semiconductor chip to said at least some of said conductive members.
Claim 4
Dependent Claim
25 words
The electronic package of claim 1 wherein said circuitized substrate further comprises a layer of flexible film dielectric and at least one electrically conductive layer.
Claim 5
Dependent Claim
31 words
The electronic package of claim 3 further including a plurality of tape leads, said tape leads electrically coupling said first semiconductor chip to said at least some of said conductive members.
Claim 6
Dependent Claim
23 words
The electronic package of claim 1 wherein said heatsink attached to said circuitized substrate is in thermal contact with said second semiconductor chip.
Claim 7
Dependent Claim
51 words
The electronic package of claim 5 wherein said first semiconductor chip is positioned adjacent and in thermal contact with said heatsink, and said second semiconductor chip is positioned adjacent and in thermal contact with said first semiconductor chip thereby being in thermal contact with said heatsink through said first semiconductor chip.
Claim 8
Dependent Claim
18 words
The electronic package of claim 1 wherein said second semiconductor chip is smaller than said first semiconductor chip.
Claim 9
Dependent Claim
27 words
The electronic package of claim 1 further including a plurality of electrically conductive elements, said elements electrically coupling said second semiconductor chip to said first semiconductor chip.
Claim 10
Dependent Claim
14 words
The electronic package of claim 8 wherein said electrically conductive elements are solder bumps.
Claim 11
Dependent Claim
14 words
The electronic package of claim 8 wherein said electrically conductive elements are gold bumps.
Claim 12
Dependent Claim
19 words
The electronic package of claim 8 wherein said plurality of electrically conductive elements are arranged in a rectangular array.
Claim 13
Dependent Claim
24 words
The electronic package of claim 1 wherein said first semiconductor chip is a processor chip and said second semiconductor chip is a memory chip.
Claim 14
Dependent Claim
25 words
The electronic package of claim 1 further including a plurality of solder members positioned on and electrically connected to respective ones of said conductive members.
Claim 15
Dependent Claim
13 words
The electronic package of claim 13 wherein said solder members are solder balls.
Claim 16
Dependent Claim
13 words
The electronic package of claim 13 wherein said solder members are solder columns.
Claim 17
Dependent Claim
27 words
The electronic package of claim 1 further including a quantity of encapsulant material positioned on and substantially covering said first semiconductor chip and said second semiconductor chip.
Claim 18
Dependent Claim
25 words
The electronic package of claim 1 , further comprising a plurality of second semiconductor chips positioned on said first semiconductor chip and electrically coupled thereto.
Claim 19
Dependent Claim
26 words
The electronic package of claim 1 , wherein said first semiconductor chip is a silicon chip and said second semiconductor chip is a gallium arsenide chip.
Claim 20
Dependent Claim
24 words
The electronic package of claim 1 , further including a plurality of metal balls or columns attached to respective ones of said conductive members.
Claim 21
Dependent Claim
15 words
The electronic package of claim 19 , wherein said metal balls or columns are copper.
Claim 22
Dependent Claim
22 words
The electronic package of claim 1 , further comprising a second conductive substrate and wherein said circuitized substrate is electrically coupled thereto.
Claim 23
Dependent Claim
17 words
The electronic package of claim 21 , wherein said second conductive substrate is a printed circuit board.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |