Semiconductor chip package with enhanced thermal conductivity

Claim 1

A semiconductor chip package comprising: a ceramic substrate including first and second opposing surfaces and at least one hole extending through said substrate to interconnect said first and second opposing surfaces; a first thermally and electrically conductive layer located on said first surface of said substrate; a second thermally and electrically conductive layer located on said second surface of said substrate and serving as a ground plane for said package; a semiconductor chip located on said first thermally and electrically conductive layer in a thermally coupled manner; a layer of circuitry located on said first surface of said substrate at a predetermined distance from said first thermally and electrically conductive layer and electrically isolated from said first thermally and electrically conductive layer, said semiconductor chip being electrically coupled to said layer of circuitry; at least one thermally and electrically conductive member located within said hole of said substrate for thermally coupling said first and second thermally and electrically conductive layers such that heat generated by said semiconductor chip will pass from said first thermally and electrically conductive layer to said second thermally and electrically conductive layer through said thermally and electrically conductive member; and means for electrically coupling said layer of circuitry to circuitry on an external circuitized substrate.