Preventing dielectric thickening over a channel area of a split-gate transistor

Claim 2

A process for fabricating a field-effect semiconductor memory device comprising the steps of: (a) providing a structure including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region and a spaced apart source region of said device, and said channel is situated between said drain region and source region and having a drain area adjacent said drain region and having source area adjacent said source region; (ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area; (b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel; (c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and (d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area thereby said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of an electrically programmable non-volatile transistor.

Claim 3

The process as defined in claim 1, wherein growing said second thermal oxide in step (b) is performed in a manner that retains said first thickness of said first gate dielectric layer substantially unchanged.

Claim 4

The process as defined in claim 1, wherein said second thermal oxide in step (b) is grown to said third thickness and said third dielectric layer of step (c) is a deposited TEOS based silicon dioxide that is formed to have said fourth thickness that is thicker than said third thickness of said second thermal oxide.

Claim 5

The process as defined in claim 3, wherein said second thermal oxide in step (b) and said third dielectric layer of step (c) form a second gate dielectric layer that is adjacent said first gate dielectric layer.

Claim 6

The process as defined in claim 2, wherein said first gate dielectric layer of step (a) consists of a first layer of thermal oxide that is disposed on and in contact with said substrate and a second layer of TEOS based silicon dioxide that is disposed on said first layer of thermal oxide.

Claim 7

The process as defined in claim 1, wherein at least a portion of said first conductive layer is formed of conductive silicon and at least a portion of said second conductive layer is formed of conductive silicon.

Claim 8

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing an apparatus including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area; (ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area; (b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel; (c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and (d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

Claim 9

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing an apparatus including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area; (ii) a first member disposed over said drain area and over at least a portion of said drain region of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area; (b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel; (c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and (d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

Claim 10

The process as defined in claim 7 further comprising the step of: (e) forming a second conductivity type source region in said substrate so that said source region is adjacent said source area of said channel and laterally spaced apart from said drain region, thereby said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of an electrically programmable non-volatile device.

Claim 11

The process as defined in claim 7, wherein growing said second thermal oxide in step (b) is performed in a manner that retains said first thickness of said first gate dielectric layer substantially unchanged.

Claim 12

The process as defined in claim 1, wherein said second thermal oxide in step (b) is grown to said third thickness and said third dielectric layer of step (c) is a deposited TEOS based silicon dioxide that is formed to have said fourth thickness that is thicker than said third thickness of said second thermal oxide.

Claim 13

The process as defined in claim 8, wherein said first gate dielectric layer of step (a) consists of a first layer of thermal oxide that is disposed on and in contact with said substrate and a second layer of TEOS based silicon dioxide that is disposed on said first layer of thermal oxide.

Claim 14

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing a structure including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area; (ii) a first member disposed over said drain area of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area; (b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel; (c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and (d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

Claim 15

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing a structure including: (i) a silicon substrate of a first conductivity type having first conductivity type first region that forms a channel region of said device that has a first surface, and a second conductivity type second region that forms a drain region of said device, and said channel having a drain area adjacent said drain region and having a source area; (ii) a first member disposed over said drain area of said substrate, said first member comprising a first gate dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first gate dielectric layer, wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said channel region and is laterally spaced apart from said drain region and is near said source area; (b) growing a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first conductive layer of said first member to a third thickness to form a thermally-grown portion of a gap-of-insulation-wall that is substantially perpendicular to said first surface of said channel region and by oxidation of said source area of the channel; (c) depositing a third dielectric layer to a fourth thickness to be in contact with and conformal to said second thermal oxide over said source area and said third dielectric also forming a deposited portion of said gap-of-insulation-wall; and (d) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over at least a portion of said source area.

Claim 16

The process as defined in claim 12 further comprising the step of: (e) forming a second conductivity type source region in said substrate so that said source region is adjacent said source area of said channel and laterally spaced apart from said drain region, thereby said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of an electrically programmable non-volatile device.

Claim 17

The process as defined in claim 12, wherein growing said second thermal oxide in step (b) is performed in a manner that retains said first thickness of said first gate dielectric layer substantially unchanged.

Claim 18

The process as defined in claim 1, wherein said second thermal oxide in step (b) is grown to said third thickness and said third dielectric layer of step (c) is a deposited TEOS based silicon dioxide that is formed to have said fourth thickness that is thicker than said third thickness of said second thermal oxide.

Claim 19

The process as defined in claim 13, wherein said first gate dielectric layer of step (a) consists of a first layer of thermal oxide that is disposed on and in contact with said substrate and a second layer of TEOS based silicon dioxide that is disposed on said first layer of thermal oxide.

Claim 20

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing a structure including: (i) a semiconductor substrate of a first-conductivity type having first-conductivity type first region that has a first surface, a first area and an adjacent second area, and a first second-conductivity type second region; (ii) a first member disposed over first area of said first region and comprising a first dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first dielectric layer wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said first conductivity type first region and said first sidewall is laterally spaced apart from said second-conductivity type second region and is adjacent said first-conductivity type second area; (b) growing and retaining a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first-conductive layer to a third thickness and by oxidation of said first-conductivity type second area; and (c) depositing a third dielectric layer to be in permanent contact with and conformal to said second thermal oxide to form a first gap-of-insulation-wall that is perpendicular to said first surface of said first-conductivity type first region of said substrate and so that said first gap-of-insulation-wall is in contact with said first sidewall of said first conductive layer; (d) forming a second second-conductivity type second region to form a source region in said substrate so that said source region is adjacent said second area and is laterally spaced apart from said first second-conductivity type second region; and (e) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over said second area, thereby said first second-conductivity type second region forms a drain region of said device, and said first conductivity type first region forms a channel region of said device, said first area and a second area of said channel forming drain area and source area respectively of said channel, and said first dielectric layer forms a first gate oxide, and said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of a programmable non-volatile device.

Claim 21

A process for fabricating a field-effect semiconductor device comprising the steps of: (a) providing a structure including: (i) a semiconductor substrate of a first-conductivity type having first-conductivity type first region that has a first surface, a first area and an adjacent second area, and a first second-conductivity type second region; (ii) a first member disposed over first area of said first region and comprising a first dielectric layer having a first thickness disposed on said substrate, and a first conductive layer disposed on said first dielectric layer wherein said first conductive layer having sidewalls including a first sidewall that is disposed over and insulated from said first conductivity type first region and said first sidewall is laterally spaced apart from said second-conductivity type second region and is adjacent said first-conductivity type second area; (b) growing and retaining a second dielectric of thermal oxide by oxidation of at least said first sidewall of said first-conductive layer to a third thickness and by oxidation of said first-conductivity type second area; and (c) depositing a third dielectric layer to be in permanent contact with and conformal to said second thermal oxide to form a first gap-of-insulation-wall that is perpendicular to said first surface of said first-conductivity type first region of said substrate and so that said first gap-of-insulation-wall is in contact with said first sidewall of said first conductive layer; (d) forming a second second-conductivity type second region to form a source region in said substrate so that said source region is adjacent said second area and is laterally spaced apart from said first second-conductivity type second region; and (e) forming a second conductive layer to be disposed over said first conductive layer in a manner to be insulated therefrom, and said second conductive layer is also formed to be in contact with said gap-of-insulation-wall including at the location that is opposite said first sidewall of said first conductive layer and in contact with said third dielectric layer over said second area, thereby said first second-conductivity type second region forms a drain region of said device, and said first conductivity type first region forms a channel region of said device, said first area and a second area of said channel forming drain area and source area respectively of said channel, and said first dielectric layer forms a first gate oxide, and said first conductive layer and said second conductive layer forming a floating gate and a control gate respectively of a programmable non-volatile device.

Claim 22

The process as defined in claim 17, wherein said second thermal oxide of step (b) and said third dielectric of step (c) form a second gate oxide that is adjacent said first gate oxide.

Claim 23

The process as defined in claim 18, wherein said second thermal oxide of step (b) is grown to a first thickness and said third dielectric of step ( c) is a TEOS based deposited oxide that is thicker than said first thickness of said second thermal oxide that is disposed on said first layer of thermal oxide.

Claim 24

The process as defined in claim 17 wherein said growth of said second oxide at said first conductivity type second area of said substrate is carried out at a temperature of less than 875° C. in a wet oxidation process.

Claim 25

The process as defined in claim 17 wherein said first dielectric layer is capable of exhibiting electric charge transport between said first conductive layer and said substrate.

Claim 26

The process as defined in claim 17 wherein said first dielectric layer transports tunneling current between one of said conductivity type second regions and said first conductive layer.

Claim 27

The process as defined in claim 17 wherein said first dielectric layer is under 250 angstroms thick.

Claim 28

The process as defined in claim 17 wherein said second conductivity type second regions of said substrate are formed by implanting ions.

Claim 29

The process as defined in claim 17 herein one of said second regions is doped with an n-type dopant to a first level of doping and the other of said second regions is doped with an n-type dopant to a second level of doping, said first level of doping being different from said second level of doping.

Claim 30

The process as defined in claim 17 wherein one of said second regions is doped with an n-type dopant to a first depth of doping and the other of said second regions is doped with an n-type dopant to a second depth of doping, said first depth of doping being different from said second depth of doping.

Claim 31

The process as defined in claim 17 wherein one of said second regions is doped with an n-type dopant to a first level of doping and the other of said second regions is doped with an n-type dopant to a second level of doping, said first level of doping being higher than said second level of doping and wherein said second region with higher level of doping forms a drain of programmable field-effect transistor (FET) and said second regions with lower level of doping forms a source of said programmable FET.

Claim 32

The process as defined in claim 17 wherein one of said second regions is doped with an n-type dopant to a first depth of doping and the other of said second regions is doped with an n-type dopant to a second depth of doping, said first depth of doping being deeper than said second depth of doping and wherein said second region with deeper depth of doping form drains of a programmable field-effect transistor (FET) and said second region with shallower depth of doping forms a source of said programmable FET.

Claim 33

The process as defined in claim 17 further comprising the step of forming at least one spacer along said first conductive layer before the formation of said control gate, and permanently retaining at least a portion of said spacer under said control gate with a thin insulator there between, whereby said thin insulator is disposed over and in contact with said spacer and said thin insulator is disposed under and in contact with said control gate.

Claim 34

The process as defined in claim 17 wherein one of said second regions is doped with an n-type dopant to a first level of doping and the other of said second regions is doped with an n-type dopant to a second level of doping, said first level of doping being different from said second level of doping, and said substrate is a monocrystalline silicon that is p-type doped.

Claim 35

The process as defined in claim 17 wherein one of said second regions is doped with an n-type dopant to a first depth of doping and the other of said second regions is doped with an n-type dopant to a second depth of doping, said first depth of doping being different from said second depth of doping, and said silicon substrate is p-type doped.