Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array

Claim 1

A method of manufacturing a split-gate memory transistor containing a floating gate comprising: implanting impurities layer of a first conductivity type onto semiconductor substrate of a second conductivity type; forming a first insulator layer on said impurities layer; forming a first photoresist layer over said first insulator, forming a first opening in said first photoresist pattern to expose a channel area; etching through said first insulator layer, said impurities layer and through portion of said substrate to form a trenched channel area having a drain impurities region extending laterally away from a first edge of said trenched channel area and a source impurities region extending laterally away from a second edge of said trenched channel area, said impurities regions separated laterally from each other; removing said first photoresist; forming a second insulator layer over the entire structure; forming a nitride film over said substrate and over said second insulator, a first opening being formed in said nitride film to expose both a drain area of said trenched channel area and a first portion of said second insulator covering said drain impurities region of said transistor; forming a first polysilicon layer over the entire structure and etching said first polysilicon layer so as to remove it from all areas except over said drain area of said trenched channel to form a floating gate; removing said nitride film to expose a surface of said second insulator over a source area of said trenched channel area and to expose the surface of said second insulator over said source region, said source area extends laterally between said drain area and said source region; forming a second photoresist layer over said second insulator to overlap said drain and source regions; etching said second insulator over said source area to expose said source area; removing said second photoresist; forming a third insulator layer over the entire structure; and forming a second polysilicon layer control gate over said third insulator to insulate said source area and said floating gate from said control gate.

Claim 2

A method of manufacturing a split-gate memory transistor containing a floating gate comprising: implanting impurities layer of a first conductivity type onto semiconductor substrate of a second conductivity type; forming a first insulator layer on said impurities layer; forming a first photoresist layer over said first insulator, forming a first opening in said first photoresist pattern to expose a channel area; etching through said first insulator layer, said impurities layer and through portion of said substrate to form a trenched channel area having a drain impurities region extending laterally away from a first edge of said trenched channel area and a source impurities region extending laterally away from a second edge of said trenched channel area, said impurities regions separated laterally from each other; removing said first photoresist; forming a second insulator layer over the entire structure; forming a nitride film over said substrate and over said second insulator, a first opening being formed in said nitride film to expose both a drain area of said trenched channel area and a first portion of said second insulator covering said drain impurities region of said transistor; forming a first polysilicon layer over the entire structure and etching said first polysilicon layer so as to remove it from all areas except over said drain area of said trenched channel to form a floating gate; removing said nitride film to expose a surface of said second insulator over a source area of said trenched channel area and to expose the surface of said second insulator over said source region, said source area extends laterally between said drain area and said source region; forming a second photoresist layer over said second insulator to overlap said drain and source regions; etching said second insulator over said source area to expose said source area; removing said second photoresist; forming a third insulator layer over the entire structure; and forming a second polysilicon layer control gate over said third insulator to insulate said source area and said floating gate from said control gate.

Claim 6

A method of forming an array of self aligned non-volatile programmable memory cells having N horizontal rows and M vertical columns on a semiconductor substrate comprising: (a) forming a first plurality of conductive continuous elongated parallel strips of impurities regions within said substrate so that said impurities strips are oriented vertically; (b) forming a second plurality of continuous elongated parallel strips of conductive material that are insulatively disposed over said substrate and are oriented vertically, said second strips being self-aligned to corresponding defining edges of said first elongated parallel strips of conductive material; and (c) forming at least one gap in each of said second continuous strips thereby forming electrically isolated floating gates from said second continuous elongated strips of conductive material.

Claim 7

A method of forming an array of self aligned non-volatile programmable memory cells having N horizontal rows and M vertical columns on a semiconductor substrate comprising: (a) forming a first plurality of conductive continuous elongated parallel strips of impurities regions within said substrate so that said impurities strips are oriented vertically; (b) forming a second plurality of continuous elongated parallel strips of conductive material that are insulatively disposed over said substrate and are oriented vertically, said second strips being self-aligned to corresponding defining edges of said first elongated parallel strips of conductive material; and (c) forming at least one gap in each of said second continuous strips thereby forming electrically isolated floating gates from said second continuous elongated strips of conductive material.