EP0282023A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1988-03-09
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Granted: —
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Expires: 2008-03-09
Abstract
Abstract Disclosed is a semiconductor memory device containing a number of memory cells each having a floating gate (13), an erase gate (15), and a control gate (17). In a data erasure mode, electrons are discharged from the floating gate (13) into the erase gate (15). In the semiconductor memory device, an impurity concentration in at least a region of the floating gate (13) overlapping with the erase gate (15) is lower than that of the erase gate (15).
Inventors
- 👤 Shinichi C/O Patent Division Tanaka
- 👤 Masayuki C/O Patent Division Hori
- 👤 Kazunori C/O Patent Division Kanebako
- 👤 Noriyoshi C/O Patent Division Tozawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 00:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
A semiconductor memory device, characterized by a semiconductor substrate (10) of a first conductivity type; a floating gate (12) containing an impurity at a predetermined concentration and layered on a first insulating film (13) which is also layered on said substrate; an erase gate (15) layered above said floating gate (13), with a second insulating film (14) interlaid therebetween, a part of said erase gate overlapping with said floating gate, and said erase gate containing impurity at a predetermined concentration; and a control gate (17) layered above said floating gate (13), with a third insulating film (14, 16) interlaid therebetween; characterized in that an impurity concentration in at least a part (13A) of said floating gate (13) overlapping with the erase gate (15) is lower than that of said erase gate (15).
Claim 2
Dependent Claim
132 words
A semiconductor memory device, characterized by a semiconductor substrate (10) of a first conductivity type; a floating gate (12) containing an impurity at a predetermined concentration and layered on a first insulating film (13) which is also layered on said substrate; an erase gate (15) layered above said floating gate (13), with a second insulating film (14) interlaid therebetween, a part of said erase gate overlapping with said floating gate, and said erase gate containing impurity at a predetermined concentration; and a control gate (17) layered above said floating gate (13), with a third insulating film (14, 16) interlaid therebetween; characterized in that an impurity concentration in at least a part (13A) of said floating gate (13) overlapping with the erase gate (15) is lower than that of said erase gate (15).
Claim 3
Dependent Claim
31 words
A semiconductor memory device according to claim 1, characterized in that an impurity concentration in the whole of said floating gate (13) is lower than that of said erase gate (15).
Claim 4
Dependent Claim
44 words
A semiconductor memory device according to claim 1, characterized in that an impurity concentration in said erase gate (15) is 6 x 10²⁰/cm³ or more, and an impurity concentration in said part (13A) of said floating gate (13) is less than 6 x 10²⁰/cm³.
Claim 5
Dependent Claim
44 words
A semiconductor memory device according to claim 2, characterized in that an impurity concentration in said erase gate (15) is 6 x 10²⁰/cm³ or more, and an impurity concentration in the whole of said said floating gate (13) is less than 6 x 10²⁰/cm³.
Claim 6
Dependent Claim
50 words
A semiconductor memory device according to claim 1, characterized in that said floating gate (13), said erase gate (15) , and said control gate (17) are made of polysilicon, and the impurity contained in said floating gate (13) , said erase gate (15) and said control gate (17) is phosphorus.
Claim 7
Dependent Claim
49 words
A semiconductor memory device according to claim 1, characterized in that said floating gate (13), said erase gate (15), and said control gate (17) are made of polysilicon, and the impurity contained in said floating gate (13) , said erase gate (15) and said control gate (17) is arsenic.
Claim 8
Dependent Claim
49 words
A semiconductor memory device according to claim 2, characterized in that said floating gate (13), said erase gate (15), and said control gate (17) are made of polysilicon, and the impurity contained in said floating gate (13) , said erase gate (15), and said control gate (17) is phosphorus.
Claim 9
Dependent Claim
49 words
A semiconductor memory device according to claim 2, characterized in that said floating gate (13), said erase gate (15), and said control gate (17) are made of polysilicon, and the impurity contained in said floating gate (13) , said erase gate (15), and said control gate (17) is arsenic.
Claim 10
Dependent Claim
43 words
A semiconductor memory device according to claim 1, characterized in that an insulating film having a three-layered structure consisting of an oxide film, a nitride film, and an oxide film is interlaid between said erase gate (15) and said control gate (17) .
Claim 11
Dependent Claim
31 words
A semiconductor memory device according to claim 1, characterized in that said erase gate (15) is laid over said control gate (17), with said third insulating film (14, 16) interlaid therebetween.
Claim 12
Dependent Claim
37 words
A semiconductor memory device according to claim 1, characterized in that said third insulating film (14, 16) has a three-layered structure consisting of oxide film (14, 16A) , a nitride film (16B), and an oxide film (1⁶C).
References Cited (Backward Citations)
No citation records indexed.
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