US4380113A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating a high capacity memory cell
Assignee: Signetics Corp
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Filing: 1980-11-17
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Granted: 1983-04-19
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Expires: 2000-11-17
Abstract
Abstract A method of fabricating an array of high capacity memory cells comprises patterning a semiconductor surface to form memory cell areas; covering the memory cell areas with insulator; forming an ion layer of first conductivity type throughout the insulator; forming an ion layer of second conductivity type throughout the semiconductor surface; forming a first conductive pattern over the insulating layer to form a storage gate and to define a storage region extending to an isolation region and to define a transfer region spaced from the isolation region by the storage region; removing ions of first conductivity type from the portion of insulator above the transfer region and from other active areas; removing ions of second conductivity type from the transfer region and other active areas; diffusing ions of first conductivity type from the insulating layer to the storage region to produce in the storage region a shallow ion layer of first conductivity type and a deep ion layer of second conductivity type; and forming a second conductivity pattern over the transfer region to define a bit line region spaced from the storage region by a portion of the transfer region and to produce a transfer gate overlying the transfer region portion and also insulated from and partially overlying the storage gate.
Inventors
- 👤 Manohar L. Malwah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:29
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10W; H10W20/00; H10W20/01; H10W20/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
301 words
A method of fabricating a high capacity memory cell, comprising: (a) forming isolation regions in a surface of a semiconductor substrate patterned to produce a multiplicity of cell areas; (b) forming an insulating layer over the entire surface of said cell areas; (c) introducing ions having majority carriers of first conductivity type throughout the entire area of said insulating layer; (d) introducing ions having majority carriers of second conductivity type opposite said first conductivity type throughout the entire area of the semiconductor surface. (e) forming a first pattern of conductive material over said insulating layer to form a storage gate and to define a storage region beneath said storage gate extending to an isolation region and to define a transfer region spaced from said isolation region by said storage region; (f) removing said insulating layer from the portion lying above said transfer region and from other active areas to selectively remove ions having majority carriers of said first conductivity type; (g) removing ions having majority carriers of said second conductivity type from said transfer region and other active areas by forming an oxide layer on the semiconductor surface where said insulating layer is removed; (h) diffusing ions having majority carriers of said first conductivity type from said insulating layer to said storage region to produce in said storage region a shallow ion layer having majority carriers of said first conductivity type and beneath said shallow ion layer a deep ion layer having majority carriers of said second conductivity type; and (i) forming a second pattern of conductive material over said transfer region to define a bit line region spaced from said storage region by a portion of said transfer region and to produce a transfer gate overlying said transfer region portion and also insulated from and partially overlying said storage gate.
Claim 2
Independent Claim
301 words
A method of fabricating a high capacity memory cell, comprising: (a) forming isolation regions in a surface of a semiconductor substrate patterned to produce a multiplicity of cell areas; (b) forming an insulating layer over the entire surface of said cell areas; (c) introducing ions having majority carriers of first conductivity type throughout the entire area of said insulating layer; (d) introducing ions having majority carriers of second conductivity type opposite said first conductivity type throughout the entire area of the semiconductor surface. (e) forming a first pattern of conductive material over said insulating layer to form a storage gate and to define a storage region beneath said storage gate extending to an isolation region and to define a transfer region spaced from said isolation region by said storage region; (f) removing said insulating layer from the portion lying above said transfer region and from other active areas to selectively remove ions having majority carriers of said first conductivity type; (g) removing ions having majority carriers of said second conductivity type from said transfer region and other active areas by forming an oxide layer on the semiconductor surface where said insulating layer is removed; (h) diffusing ions having majority carriers of said first conductivity type from said insulating layer to said storage region to produce in said storage region a shallow ion layer having majority carriers of said first conductivity type and beneath said shallow ion layer a deep ion layer having majority carriers of said second conductivity type; and (i) forming a second pattern of conductive material over said transfer region to define a bit line region spaced from said storage region by a portion of said transfer region and to produce a transfer gate overlying said transfer region portion and also insulated from and partially overlying said storage gate.
Claim 3
Dependent Claim
14 words
The invention according to claim 1, wherein said substrate comprises second conductivity type material.
Claim 4
Dependent Claim
14 words
The invention according to claim 2 wherein said substrate comprises P type conductivity material.
Claim 5
Dependent Claim
44 words
The invention according to claim 1, wherein said second pattern of conductive material forms two transfer gates in each cell area that are spaced apart by a single bit line region, with each transfer gate spaced from an isolation region by a storage region.
Claim 6
Dependent Claim
48 words
The invention according to claim 4, wherein said second pattern of conductive material extends over a peripheral region adjacent to a cell area and forms a peripheral transfer gate spaced from an isolation region to define regions on opposite sides thereof for the formation of source and drain.
Claim 7
Dependent Claim
48 words
The invention according to claim 5, and further including introducing impurities of first conductivity type after forming said second pattern of conductive material to produce a bit line between said two transfer gates and to produce a source and drain on opposite sides of said peripheral transfer gate.
Claim 8
Dependent Claim
14 words
The invention according to claim 1, wherein said semiconductor substrate is formed of silicon.
Claim 9
Dependent Claim
33 words
The invention according to claim 7, wherein the step of (g) is performed by growing oxide over the semiconductor surface where said insulating layer is removed utilizing a low temperature, wet oxidation cycle.
Claim 10
Dependent Claim
16 words
The invention according to claim 1, wherein said conductive material in (e) and (i) is polysilicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |