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US3897625A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for the production of field effect transistors by the application of selective gettering

Assignee: Siemens AG
•
Filing: 1974-03-28
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Granted: 1975-08-05
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Expires: 1994-03-28
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Abstract

Abstract Method of making a field effect transistor having a short channel length which includes forming a protective covering layer on a silicon layer medium doped with an impurity that can be gettered, removing portions of the protective layer, forming a gettering layer on the exposed silicon surface where the portions of the protective covering has been removed, etching spaced areas of the getter layer and a portion of the protective covering adjacent one of the etched getter areas to provide source and drain diffusion windows, diffusing impurities of the opposite impurity type to the doping of the silicon layer through the windows to provide source and drain regions in the silicon layer separated by a channel region formed in its length in part by a medium doped region and in part by a low doped region, removing the protective covering from above the medium doped region, forming an insulating layer over the entire area, forming windows in the insulating layer above portions of the insulating layer above the source and drain regions, forming electrodes on the source and drain regions respectively and forming a gate electrode on the insulating layer above the highly doped channel region.

Inventors

  • 👤 Jeno Tihanyi
  • 👤 Heinrich Schloetterer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 15:39
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D86/00; H10D86/01; H10D86/03; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/053; Y10S148/15; Y10S257/00; Y10S257/913

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 144 words
A PROCESS FOR MAKING A FIELD EFFECT TRANSISTOR HAVING A SHORT CHANNEL LENGTH WHICH INCLUDES PROVIDING A LAYER OF SILICON DOPED WITH AN IMPURITY WHICH CAN BE GETTERED, COATING THE SURFACE THEREOF WITH A PROTECTIVE COVERING, ETCHING SELECTED PORTIONS OF THE PROTECTIVE COVERING AWAY TO LEAVE DEWRTAIN EXPOSED AREAS, COVERING THE EXPOSED AREAS WITH A LAYER OF GETTERING MATERIAL, THEREBY GATTERING THE REGION BELOW THE GETTERING LAYER TO REDUCE THE DOPING CONCENTRATION IN SUCH REGIONS, REMOVING PORTIONS OF THE GETTERING LAYER ABOVE THE SPACED LOW DOPANT REGIONS WHILE LEAVING A PORTION OF THE REMAINING PROTECTIVE COVERING AND A PORTION OF THE GETTERING LAYER LYING IMMEDIATELY ADJACENT THE REMAINING PROTECTIVE COVERING, DIFFUSING A DOPANT OF THE OPPOSITE IMPURITY TYPE INTO THE SAID LOW DOPANT REGIONS TO FORM SOURCE AND DRAIN REGIONS RESPECTIVELY, REMOVING THE REMAINING PROTECTIVE COVERING WHILE LEAVING THE REMAINING GETTERING LAYER, COVERING THE
Claim 2
Dependent Claim 144 words
A PROCESS FOR MAKING A FIELD EFFECT TRANSISTOR HAVING A SHORT CHANNEL LENGTH WHICH INCLUDES PROVIDING A LAYER OF SILICON DOPED WITH AN IMPURITY WHICH CAN BE GETTERED, COATING THE SURFACE THEREOF WITH A PROTECTIVE COVERING, ETCHING SELECTED PORTIONS OF THE PROTECTIVE COVERING AWAY TO LEAVE DEWRTAIN EXPOSED AREAS, COVERING THE EXPOSED AREAS WITH A LAYER OF GETTERING MATERIAL, THEREBY GATTERING THE REGION BELOW THE GETTERING LAYER TO REDUCE THE DOPING CONCENTRATION IN SUCH REGIONS, REMOVING PORTIONS OF THE GETTERING LAYER ABOVE THE SPACED LOW DOPANT REGIONS WHILE LEAVING A PORTION OF THE REMAINING PROTECTIVE COVERING AND A PORTION OF THE GETTERING LAYER LYING IMMEDIATELY ADJACENT THE REMAINING PROTECTIVE COVERING, DIFFUSING A DOPANT OF THE OPPOSITE IMPURITY TYPE INTO THE SAID LOW DOPANT REGIONS TO FORM SOURCE AND DRAIN REGIONS RESPECTIVELY, REMOVING THE REMAINING PROTECTIVE COVERING WHILE LEAVING THE REMAINING GETTERING LAYER, COVERING THE
Claim 3
Dependent Claim 17 words
A process according to claim 1, in which the silicon layer is a piece of bulk silicon.
Claim 4
Dependent Claim 24 words
A process according to claim 1, in which the layer of silicon is a layer which has been epitaxially grown on a silicon substrate.
Claim 5
Dependent Claim 18 words
A process according to claim 1, in which the silicon layer is formed on an electrically insulating substrate.
Claim 6
Dependent Claim 13 words
A process according to claim 4, in which the insulating substrate is spinel.
Claim 7
Dependent Claim 13 words
A process according to claim 4, in which the insulating substrate is sapphire.
Claim 8
Dependent Claim 18 words
A process according to claim 1, in which the gettering layer is a pyrolytically deposited silicon nitride layer.
Claim 9
Dependent Claim 18 words
A process according to claim 1, in which the gettering layer is a layer of thermic silicon oxide.
Claim 10
Dependent Claim 14 words
A process according to claim 1, in which the electrodes are formed of aluminum.
Claim 11
Dependent Claim 14 words
A process according to claim 1, in which the electrodes are formed of molybdenum.
Claim 12
Dependent Claim 17 words
A process according to claim 1, in which the electrodes are formed of highly doped polycrystalline silicon.
Claim 13
Dependent Claim 16 words
A process according to claim 1, in which the impurity in the silicon layer is boron.
Claim 14
Dependent Claim 16 words
A process according to claim 1, in which the impurity in the silicon layer is aluminum.
Claim 15
Dependent Claim 36 words
A process according to claim 3, in which the impurity is aluminum, and in which these impurities are diffused from the substrate into the silicon layer during the application of the silicon layer on the substrate.
Claim 16
Dependent Claim 36 words
A process according to claim 4, in which the impurity is aluminum, and in which these impurities are diffused from the substrate into the silicon layer during the application of the silicon layer on the substrate.

References Cited (Backward Citations)

US3490964A Cited
US3783052A Cited
US3837071A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-08-04 1979-02-03 1979-08-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-08-04 1983-02-03 1983-08-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-08-04 1987-02-03 1987-08-05 $7700.00 Window Closed / Lapsed

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