Electrically alterable read only memory cell

Claim 2

An electrically programmable and erasable MOS memory cell structure, comprising: a silicon substrate having a source, a drain and a conductive channel means connecting said source and drain; a diffused control gate region of semiconductive material separate from said conductive channel and located in the surface of said substrate; and means for connecting a source of electrical potential to said source, said drain and said diffused control gate region; a single crystal silicon oxide insulator layer overlying said diffused control gate region, said channel region and said substrate, said oxide insulator layer being thinner in the vertical direction over said diffused region and over said channel region than over other portions of said substrate; an electrically floating conductive gate means deposited on the surface of said single crystal silicon oxide layer in a zone overlying at least a portion of both said diffused control gate region and said conductive channel region; a layer of polycrystalline oxide overlying said electrically floating conductive gate; a conductive erase gate means overlying said insulating layer of polycrystalline oxide in a region generally overlying said diffused control gate region in said substrate beneath, said conductive erase gate means being supplied with an electrical contact for applying an erase voltage across said polycrystalline oxide to said floating gate means by capacitive coupling through said oxide insulator layers; said single crystal silicon oxide and said polycrystalline silicon oxide are in the areas which overly said diffused control gate and said conductive channel, respectively of thicknesses related to one another by approximately the ratio of one to four, said single crystal oxide thickness being represented by the numerator.

Claim 3

An electrically programmable and erasable MOS memory cell structure, comprising: a silicon substrate having a source, a drain and a conductive channel means connecting said source and drain; a diffused control gate region of semiconductive material separate from said conductive channel and located in the surface of said substrate; and means for connecting a source of electrical potential to said source, said drain and said diffused control gate region; a single crystal silicon oxide insulator layer overlying said diffused control gate region, said channel region and said substrate, said oxide insulator layer being thinner in the vertical direction over said diffused region and over said channel region than over other portions of said substrate; an electrically floating conductive gate means deposited on the surface of said single crystal silicon oxide insulator layer in a zone overlying at least a portion of both said diffused control gate region and said conductive channel region; a conductive programming gate means overlying said single crystal silicon oxide insulator and underlying said floating gate means in a region laterally between said control gate diffusion area and overlying at least a portion of said channel area in the surface of said oxide insulation; a layer of polycrystalline silicon oxide insulating said programming gate from said floating gate and being provided with an electrical contact for connecting a source of electrical potential thereto; and a conductive erase gate means overlying said insulating layer of polycrystalline oxide in a region generally overlying said diffused control gate region in said substrate beneath, said conductive erase gate means being supplied with an electrical contact for applying an erase voltage across said polycrystalline oxide to said floating gate means by capacitive coupling through said oxide insulator layers; said single crystal silicon oxide and said polycrystalline silicon oxide are in the areas which overly said diffused control gate and said conductive channel, respectively of thicknesses related to one another by approximately the ratio of one to four, said single crystal oxide thickness being represented by the numerator.

Claim 4

An electrically programmable and erasable MOS memory cell structure, comprising: a silicon substrate having a source, a drain and a conductive channel means connecting said source and drain; a diffused control gate region of semiconductive material separate from said conductive channel and located in the surface of said substrate; and means for connecting a source of electrical potential to said source, said drain and said diffused control gate region; a single crystal silicon oxide insulator layer overlying said diffused control gate region, said channel region and said substrate, said oxide insulator layer being thinner in the vertical direction over said diffused region and over said channel region than over other portions of said substrate; an electrically floating conductive gate means deposited on the surface of said single crystal silicon oxide insulator layer in a zone overlying at least a portion of both said diffused control gate region and said conductive channel region; a conductive programming gate means overlying said single crystal silicon oxide insulator and underlying said floating gate means in a region laterally between said control gate diffusion area and overlying at least a portion of said channel area in the surface of said oxide insulation; a layer of polycrystalline silicon oxide insulating said programming gate from said floating gate and being provided with an electrical contact for connecting a source of electrical potential thereto; and a conductive erase gate means overlying said insulating layer of polycrystalline oxide in a region generally overlying said diffused control gate region in said substrate beneath, said conductive erase gate means being supplied with an electrical contact for applying an erase voltage across said polycrystalline oxide to said floating gate means by capacitive coupling through said oxide insulator layers; said single crystal silicon oxide and said polycrystalline silicon oxide are in the areas which overly said diffused control gate and said conductive channel, respectively of thicknesses related to one another by approximately the ratio of one to four, said single crystal oxide thickness being represented by the numerator.

Claim 5

A memory cell as described in claim 1 or claim 2, wherein: the thickness of said single crystal oxide, in the areas which overly said diffused control gate and said conductive channel, respectively is approximately in the range of 40 to 50 nanometers and the thickness of said polycrystalline oxide is approximately in the range of 160 to 240 nanometers.