Method for manufacturing a mosic having self-aligned contact holes

Claim 1

A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate of a first conductivity type having a major surface including a device region at which a relatively thin insulating film is formed and a field region which surrounds the device region and at which a relatively thick insulating film is formed; forming a gate electrode having top and side walls from a doped polysilicon layer on said relatively thin insulating film with a mask provided on the top wall of said gate electrode; introducing first impurities of a second conductivity type, which is opposite in polarity to said first conductivity type, into said substrate selectively at a first dose through said relatively thin insulating film using said relatively thick insulating film as a part of a mask; forming a protective film of a material which covers the top and side walls of said gate electrode and removing said relatively thin insulating film where exposed excepting that portion of said relatively thin insulating film which underlies said gate electrode and that portion said protective film which covers the side walls of said gate electrode; introducing second impurities of said second conductivity type into said substrate selectively at a second dose using said protective film and said relatively thick insulating film as a mask to define a pair of diffusion regions, one on each side of said gate electrode; forming an overlaying insulating film across the entire surface; removing said overlying insulating film at least from said device region to thereby form at least one contact hole in said overlying insulating film immediately adjacent to a portion of said protective film in a self-aligned fashion using said protective film as a part of a mask, said protective film remaining to cover the top and side walls of said gate electrode; and forming a metal contact partly located in said contact hole to be in electrical contact with one of said pair of diffusion regions, said metal contact being electrically isolated from said gate electrode by said protective film.

Claim 2

A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate of a first conductivity type having a major surface including a device region at which a relatively thin insulating film is formed and a field region which surrounds the device region and at which a relatively thick insulating film is formed; forming a gate electrode having top and side walls from a doped polysilicon layer on said relatively thin insulating film with a mask provided on the top wall of said gate electrode; introducing first impurities of a second conductivity type, which is opposite in polarity to said first conductivity type, into said substrate selectively at a first dose through said relatively thin insulating film using said relatively thick insulating film as a part of a mask; forming a protective film of a material which covers the top and side walls of said gate electrode and removing said relatively thin insulating film where exposed excepting that portion of said relatively thin insulating film which underlies said gate electrode and that portion said protective film which covers the side walls of said gate electrode; introducing second impurities of said second conductivity type into said substrate selectively at a second dose using said protective film and said relatively thick insulating film as a mask to define a pair of diffusion regions, one on each side of said gate electrode; forming an overlaying insulating film across the entire surface; removing said overlying insulating film at least from said device region to thereby form at least one contact hole in said overlying insulating film immediately adjacent to a portion of said protective film in a self-aligned fashion using said protective film as a part of a mask, said protective film remaining to cover the top and side walls of said gate electrode; and forming a metal contact partly located in said contact hole to be in electrical contact with one of said pair of diffusion regions, said metal contact being electrically isolated from said gate electrode by said protective film.