Trench-isolated self-aligned split-gate EEPROM transistor and memory array

Claim 1

A non-volatile memory transistor formed in a substrate having a semiconductor surface portion of a first conductivity type; a source region and a drain region, each comprising a second conductivity type diffusion at the surface of said substrate having thick oxide thereover; a channel region comprising a portion of said substrate underlying an indentation therein between said source and drain regions; with said channel region comprising a source area disposed adjacent to said source region and a drain area disposed adjacent to said drain region; a thin gate insulator overlying said channel region; a sidewall dielectric layer covering the sidewalls of said indentation; a floating gate comprising a dielectrically insulated conductive layer overlying only said drain area of said channel and not overlying said drain area; with said floating gate being closer to said drain region and spaced apart from said source region by said source area; a control gate overlying and dielectrically insulated from said source area and said floating gate; with said control gate separating said floating gate from said source region;