EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells

Claim 2

An EEPROM memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N EEPROM cells organized in to M horizontally directed rows and N vertically directed columns; a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell; a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a first thin insulator, and oriented in a substantially horizontal direction, said sets forming plurality of pairs of first control lines, with each of said pairs including one first control line from said first set and one adjacent first control line from said second set, with each of said first control lines in said pairs being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell being a channel region of said given cell, with said channel region including a drain area adjacent to said drain region and a source area adjacent to said source region of said given cell; a set of M×N floating gates, with each floating gate included in a given one of the cells in said array, with each floating gate including a first section disposed below said first control line associated with a given cell and disposed over said drain area and not over said source area of said channel region, and with each floating gate including a second section spaced apart from said channel region of said given cell; and a set of second control lines, spaced apart from said channel regions in associated said given cells each of said second control lines insulatively disposed directly over said conductive bit line regions in an area of said substrate associated with memory cells of rows that are associated with one of said pairs of said first control lines and disposed over said second sections of said floating gates associated with said pair of associated first control lines.

Claim 3

The EEPROM of claim 1 wherein said first impurity bit line region in a given adjacent pair of impurity bit line regions forms drain region for at least one of said give cells associated with said first set of first control lines, and said first impurity bit line region forms source region for at least one of said given cells associated with said second set of first control lines; and said second impurity bit line region in said given adjacent pair of impurity bit line regions forms source region for at least one of said given cells associated with said first set of first control lines, and said second impurity bit line region forms drain region for at least one of said given cells associated with said second set of first control lines.

Claim 4

The EEPROM of claim 1 wherein each of said floating gates is comprised of an elongated continuous member that has a short side and a long side and wherein said first and second sections of each of said floating gates are positioned on different points along an axis that passes along the long side of said associated floating gate member and said axis is not parallel to said horizontal direction of said rows and said axis is not perpendicular to said major surface of the substrate.

Claim 5

The EEPROM of claim 1 wherein said second sections of said floating gates are arranged in groups, each of said groups includes at least two of said second sections of adjacent said floating gates, and each of said groups associated with only one of said second control lines; and each of said groups of said second sections is insulatively disposed along an integrated area of said substrate that is surrounded by, continuous with, and in contact with at least two adjacent of said bit line impurities regions and at least two adjacent of said channel regions.

Claim 6

The EEPROM of claim 1 wherein each of said floating gates is comprised of an elongated continuous member that has a short side and a long side and wherein said first and second sections of each of said floating gates are positioned on different points along an axis that passes along the long side of said associated floating gate member and said axis is not parallel to said horizontal direction of said rows and said axis is not perpendicular to said major surface of the substrate; and wherein substantially the entire upper surface of said floating gate member contains substantially the same amount of impurities.

Claim 7

An EEPROM memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N EEPROM cells organized into M horizontally directed rows and N vertically directed columns; a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell; said source region comprising a lightly doped region and a heavily doped region; said lightly doped region positioned closer to said drain; said drain region comprising a heavily doped region; a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate and directly over said bit line regions, separated therefrom by a layer of a first insulator, and oriented in a substantially horizontal direction, said sets forming plurality of pairs of first control lines, with each of said pairs including one first control line from said first set and one adjacent first control line from said second set, with each of said first control lines in said pairs being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell between said source region and said drain region being a channel region of said given cell; a set of M×N floating gates, with each floating gate included in a given one of ht cells in said array, with each floating gate including a first section disposed below said first control line associated with a given cell and disposed over said channel region, and with each floating gate including a second section spaced apart from said channel region of said given cell; and a set of second control lines, spaced apart from said channel regions in associated said given cells, each of said second control lines insulatively disposed directly over said conductive bit line regions in an area of said substrate associated with memory cells of rows that are associated with one of said pairs of said first control lines and disposed over said second sections of said floating gates associated with said pair of associated first control lines.

Claim 8

An EEPROM memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N EEPROM cells organized into M horizontally directed rows and N vertically directed columns; a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell; said source region comprising a lightly doped region and a heavily doped region; said lightly doped region positioned closer to said drain; said drain region comprising a heavily doped region; a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate and directly over said bit line regions, separated therefrom by a layer of a first insulator, and oriented in a substantially horizontal direction, said sets forming plurality of pairs of first control lines, with each of said pairs including one first control line from said first set and one adjacent first control line from said second set, with each of said first control lines in said pairs being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell between said source region and said drain region being a channel region of said given cell; a set of M×N floating gates, with each floating gate included in a given one of ht cells in said array, with each floating gate including a first section disposed below said first control line associated with a given cell and disposed over said channel region, and with each floating gate including a second section spaced apart from said channel region of said given cell; and a set of second control lines, spaced apart from said channel regions in associated said given cells, each of said second control lines insulatively disposed directly over said conductive bit line regions in an area of said substrate associated with memory cells of rows that are associated with one of said pairs of said first control lines and disposed over said second sections of said floating gates associated with said pair of associated first control lines.

Claim 9

The EEPROM of claim 6 wherein said first impurity bit line region in a given adjacent pair of impurity bit line regions forms drain region for at least one of said given cells associated with said first set of first control lines, and said first impurity bit line region forms source region for at least one of said given cells associated with said second set of first control lines; and said second impurity bit line region in said given adjacent pair of impurity bit line regions forms source region for at least one of said given cells associated with said first set of first control lines, and said second impurity bit line region forms drain region for at least one of said given cells associated with said second set of first control lines.

Claim 10

The EEPROM of claim 6 wherein each of said floating gates is comprised of an elongated continuous member that has a short side and a long side and wherein said first and second sections of each of said floating gates are positioned on different points along an axis that passes along the long side of said associated floating gate member and said axis is not parallel to said horizontal direction of said rows and said axis is not perpendicular to said major surface of the substrate.

Claim 11

The EEPROM of claim 6 wherein each of said floating gates is comprised of an elongated continuous member that has a short side and a long side and wherein said first and second sections of each of said floating gates are positioned on different points along an axis that passes along the long side of said associated floating gate member and said axis is not parallel to said horizontal direction of said rows and said axis is not perpendicular to said major surface of the substrate; and wherein substantially the entire upper surface of said floating gate member contains substantially the same amount of impurities.

Claim 12

The EEPROM of claim 6 wherein said second sections of said floating gates are arranged in groups, each of said groups includes at least two of said second sections of adjacent said floating gates, and each of said groups associated with only one of said second control lines; and each of said groups of said second sections is insulatively disposed along an integrated area of said substrate that is surrounded by, continuous with, and in contact with at least two adjacent of said bit line impurities regions and at least two adjacent of said channel regions.

Claim 13

The EEPROM of claim 6 wherein a given memory cell of said array further comprising: said floating gate being disposed over a gate oxide with a gate oxide thickness; said gate oxide being disposed over said channel region and over an under-diffused portion of an associated said impurity bit line region, said under-diffused portion disposed directly under said floating gate; a first portion of said first insulator is disposed between associated said first control line and associated said impurity bit line regions to form bit-line oxide, said bit line oxide having a second thickness, and said bit-line oxide is not disposed under said floating gate; said bit-line oxide being at least partially comprised of a thermal oxide is in contact with said floating gate; and said bit-line oxide is formed to said second thickness while keeping said gate oxide thickness substantially uniform so that said gate oxide thickness over said channel region is equal to the thickness of said gate oxide over said under-diffused region thereby improving operation of said memory cell.

Claim 14

The EEPROM array of claim 11 wherein said bit-line oxide comprises at least one layer of thermal oxide that is disposed under at least one oxide layer that is not a thermal oxide.

Claim 15

An architecture for a programmable non-volatile memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N programmable non-volatile cells organized into M rows and N columns; a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a thin insulator, and oriented in a substantially horizontal direction, with each of said first control lines being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell being a channel region of said given cell, with said channel region disposed between said drain region and said source region of said given cell; a set of bit line diffusions of a second conductivity type integrally formed along the major surface of said substrate, each constituting a conductor that is continuous with and joining at least three of said rows, said bit line diffusions forming plurality of adjacent pairs of bit line diffusions, each pair with: i) a first bit line diffusion in a given pair of adjacent bit line diffusions forming a drain region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a source region for said given cell associated with said second set of said first control lines, ii) said first bit line diffusion in a given pair of adjacent bit line diffusions forming a source region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a drain region for said given cell associated with said second set of said first control lines; and a set of M×N polysilicon floating gates, with each floating gate included in a given one of the cells in said array, with each floating gate disposed below the word line conductor associated with said given cell and disposed over at least a portion of said channel area.

Claim 16

An architecture for a programmable non-volatile memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N programmable non-volatile cells organized into M rows and N columns; a first set of first control lines and a second set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a thin insulator, and oriented in a substantially horizontal direction, with each of said first control lines being exclusively associated with a given row in said array and with the substrate area disposed below said first control line associated with a given cell being a channel region of said given cell, with said channel region disposed between said drain region and said source region of said given cell; a set of bit line diffusions of a second conductivity type integrally formed along the major surface of said substrate, each constituting a conductor that is continuous with and joining at least three of said rows, said bit line diffusions forming plurality of adjacent pairs of bit line diffusions, each pair with: i) a first bit line diffusion in a given pair of adjacent bit line diffusions forming a drain region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a source region for said given cell associated with said second set of said first control lines, ii) said first bit line diffusion in a given pair of adjacent bit line diffusions forming a source region for a given cell associated with said first set of first control lines and a second bit line diffusion in said given pair forming a drain region for said given cell associated with said second set of said first control lines; and a set of M×N polysilicon floating gates, with each floating gate included in a given one of the cells in said array, with each floating gate disposed below the word line conductor associated with said given cell and disposed over at least a portion of said channel area.

Claim 17

The memory architecture of claim 13 wherein: the floating gates associated with said first set of first control lines form first floating gates vertical columns; the floating gates associated with said second set of first control lines form second floating gates vertical columns; and said first floating gates vertical columns are not in columnar alignment with said second floating gates vertical columns.

Claim 18

A programmable non-volatile memory, formed on a semiconductor substrate having a major surface, said memory comprising: an array of M×N electrically writable and electrically readable non-volatile memory cells organized into M rows oriented along a first axis and N rows oriented along a second axis that is orthogonal to said first axis; a first set of charge emitting control means and a second set of charge emitting control means oriented along said first axis, said sets forming plurality of pairs of charge emitting control means, with each of said pairs including one charge emitting control means from said first set and one adjacent charge emitting control means from said second set, with each of said charge emitting control means in said pairs being associated with plurality of memory cells only within a given one of said M rows in said array; a set of second control lines organized so that each of said second control lines insulatively disposed along said substrate, only associated with a corresponding one of said pairs of charge emitting control means, and associated with at least one of said memory cells in each of said M rows that are associated with said corresponding pair of first charge emitting control means; and each of said charge emitting means is the only conductor means that is connected to plurality of memory cells within said given one of said M rows of said array and is not connected to adjacent one of said M rows.

Claim 19

A programmable non-volatile memory, formed on a semiconductor substrate having a major surface, said memory comprising: an array of M×N electrically writable and electrically readable non-volatile memory cells organized into M rows oriented along a first axis and N rows oriented along a second axis that is orthogonal to said first axis; a first set of charge emitting control means and a second set of charge emitting control means oriented along said first axis, said sets forming plurality of pairs of charge emitting control means, with each of said pairs including one charge emitting control means from said first set and one adjacent charge emitting control means from said second set, with each of said charge emitting control means in said pairs being associated with plurality of memory cells only within a given one of said M rows in said array; a set of second control lines organized so that each of said second control lines insulatively disposed along said substrate, only associated with a corresponding one of said pairs of charge emitting control means, and associated with at least one of said memory cells in each of said M rows that are associated with said corresponding pair of first charge emitting control means; and each of said charge emitting means is the only conductor means that is connected to plurality of memory cells within said given one of said M rows of said array and is not connected to adjacent one of said M rows.

Claim 20

In an EEPROM array, having a plurality of bit lines oriented parallel to a vertical axis and plurality of word lines oriented parallel to a horizontal axis, with said array including N×M EEPROM cells formed along a major surface of a semiconductor substrate of a first conductivity type, an architecture for said array comprising: four floating gates, with each of said floating gates included in a corresponding EEPROM cell and with each floating gate comprised of an elongated member that has a short side and a long side, said floating gate member having a programming section and an erase section disposed along an individual axis, wherein said individual axis of each of said floating gates member passes along said long side of a corresponding floating gate, and said corresponding individual axis is not parallel to said horizontal axis of said word lines and is not perpendicular to the surface of said substrate; said programming section of each of said floating gates being disposed over at lest a portion of a corresponding channel region of a field effect transistor that is formed in said substrate and all said programming section is separated from said channel region by only an insulator that has a dielectric constant; an erase conductor structure having erase regions coupled by connecting regions, with said four floating gates oriented so that the erase sections of said floating gates are insulatively disposed under said erase regions; and said four corresponding EEPROM cells connect to a first bit line region of a second conductivity type that is integrally formed within said substrate; whereby at least a portion of said first bit line region of said second conductivity type is insulatively disposed directly under at least a portion of said erase conductor structure.

Claim 21

In an EEPROM array, having a plurality of bit lines oriented parallel to a vertical axis and plurality of word lines oriented parallel to a horizontal axis, with said array including N×M EEPROM cells formed along a major surface of a semiconductor substrate of a first conductivity type, an architecture for said array comprising: four floating gates, with each of said floating gates included in a corresponding EEPROM cell and with each floating gate comprised of an elongated member that has a short side and a long side, said floating gate member having a programming section and an erase section disposed along an individual axis, wherein said individual axis of each of said floating gates member passes along said long side of a corresponding floating gate, and said corresponding individual axis is not parallel to said horizontal axis of said word lines and is not perpendicular to the surface of said substrate; said programming section of each of said floating gates being disposed over at lest a portion of a corresponding channel region of a field effect transistor that is formed in said substrate and all said programming section is separated from said channel region by only an insulator that has a dielectric constant; an erase conductor structure having erase regions coupled by connecting regions, with said four floating gates oriented so that the erase sections of said floating gates are insulatively disposed under said erase regions; and said four corresponding EEPROM cells connect to a first bit line region of a second conductivity type that is integrally formed within said substrate; whereby at least a portion of said first bit line region of said second conductivity type is insulatively disposed directly under at least a portion of said erase conductor structure.

Claim 22

The architecture of the EEPROM array of claim 16 further comprising: said erase sections of said floating gates are arranged in groups, each of said groups includes at least two of said erase sections of adjacent said floating gates, and each of said groups associated with said erase conductor structure; and each of said groups of said erase sections is insulatively disposed along an integrated area of said substrate that is surrounded by, continuous with, and in contact with at least two adjacent of said second conductivity type regions and at least two adjacent of said channel regions.

Claim 23

The EEPROM of claim 16 wherein said first and second sections of each of said floating gate members are positioned on different points along an axis that passes along the long side said associated floating gate member and said axis is in parallel to said vertical direction of said bit lines and substantially parallel to said major surface of said substrate; and wherein substantially the entire surface of said floating gate contains substantially the same amount of impurities.

Claim 24

The EEPROM of claim 16 further comprising means for connecting plurality of said second conductivity type bit line regions that are formed along said vertical axis.

Claim 25

The EEPROM of claim 19 wherein said means for connecting is a conductor of said second conductivity type and is formed in said substrate.

Claim 26

The EEPROM of claim 19 wherein said means is a metal conductor.

Claim 27

The EEPROM of claim 19 wherein said means is a conductor of said second conductivity type and is formed in said substrate to connect between adjacent said second conductivity type regions and wherein a metal conductor connects to said second conductivity type regions that are not adjacent, thereby reducing the electrical resistance along said bit line.

Claim 28

The EEPROM of claim 16 further comprising means for connecting plurality of said erase conductor structures in a direction that is parallel to said vertical axis of the bit lines or in parallel to said horizontal axis of the rows.

Claim 29

The EEPROM of claim 16 wherein each of said floating gates is comprised of an elongated continuous member that has a short side and a long side and wherein said first and second sections of each of said floating gates are positioned on different points along an axis that passes along the long side of said associated floating gate member and said axis is parallel to said vertical bit line axial direction and is not perpendicular to said surface of said substrate.

Claim 30

A programmable non-volatile memory transistor formed along a semiconductor substrate of a first conductivity type comprising: a floating gate structure disposed over a first region of said substrate, said floating gate structure including a first dielectric layer having a first thickness disposed over said substrate, a first conductive gate member having a chemically engraved surface disposed over said first dielectric layer and said floating gate structure also including a second dielectric layer disposed over and conformal with at least a portion of said engraved surface of said first conductive gate member; first impurities of a second conductivity type integrally formed along two spaced-apart second regions of said substrate, each of said second region extending from said first region; and a second conductive control gate member disposed over and conformal with said second dielectric layer, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said second conductive control gate member in all modes of operations of said memory transistor, and said structure also increases the capacitance between said first and second conductive gate members and thereby reduces the operating voltage of said memory cell under the operating voltage condition of said memory cell.

Claim 31

A programmable non-volatile memory transistor formed along a semiconductor substrate of a first conductivity type comprising: a floating gate structure disposed over a first region of said substrate, said floating gate structure including a first dielectric layer having a first thickness disposed over said substrate, a first conductive gate member having a chemically engraved surface disposed over said first dielectric layer and said floating gate structure also including a second dielectric layer disposed over and conformal with at least a portion of said engraved surface of said first conductive gate member; first impurities of a second conductivity type integrally formed along two spaced-apart second regions of said substrate, each of said second region extending from said first region; and a second conductive control gate member disposed over and conformal with said second dielectric layer, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said second conductive control gate member in all modes of operations of said memory transistor, and said structure also increases the capacitance between said first and second conductive gate members and thereby reduces the operating voltage of said memory cell under the operating voltage condition of said memory cell.

Claim 32

The memory transistor as defined in claim 25 wherein said first conductive gate member is comprised of polycrystalline silicon.

Claim 33

The memory transistor as defined in claim 25 wherein said first conductive gate member is comprised of polycrystalline silicon.

Claim 34

The memory transistor as defined in claim 25 wherein said first thin dielectric is comprised of silicon dioxide.

Claim 35

The memory transistor as defined in claim 25 wherein said first thin dielectric layer is capable of exhibiting electric charge transport between said first conductive gate member and said substrate.

Claim 36

The memory transistor as defined in claim 25 wherein the thickness of said first dielectric layer is unified so that the thickness over said channel region is equal to the thickness over said under-diffused substrate region of said first impurities.

Claim 37

The memory transistor as defined in claim 25 further comprising at least one spacer disposed alongside said first conductive gate member, said spacer is not disposed over said first region of said substrate and wherein said spacer comprising: a first portion comprised of a thermal oxide that is in contact with said first conductive gate member; and a second portion that includes a material that is not thermal oxide.

Claim 38

The memory transistor as defined in claim 25 wherein said second dielectric comprising oxide and nitride.

Claim 39

The memory transistor as defined in claim 25 wherein said second dielectric layer is capable of exhibiting a bulk-limited Frenkel-Poole type of electron conduction.

Claim 40

The memory transistor of claim 25 wherein: said first conductive gate member defining an edge of at least one of said spaced-apart second regions of said substrate alongside said first conductive gate member; and said first impurities are formed to be self-aligned with said first conductive gate member, and at least one of said first impurities forming an under-diffused substrate region under a portion of said first conductive gate member.

Claim 41

The memory transistor as defined in claim 34 wherein a first of said second regions is doped with an n-type dopant to a first level of doping and the second of said second regions is doped with an n-type dopant to a second level of doping, said first level of doping being different from said second level of doping.

Claim 42

The memory transistor as defined in claim 34 wherein a first of said second regions is doped with an n-type dopant to a first depth of doping and the second of said second regions is doped with an n-type dopant to a second depth of doping, said first depth of doping being different from said second depth of doping.

Claim 43

The memory transistor as defined in claim 34 wherein a first of said second regions is doped with an n-type dopant to a first level of doping and the second of said second regions is doped with an n-type dopant to a second level of doping, said first level of doping being higher than said second level of doping and wherein said second region with higher level of doping forms drain region of said programmable transistor and said second region with lower levels of doping forms a source region of said programmable transistor.

Claim 44

The memory transistor as defined in claim 34 wherein a first of said second regions is doped with an n-type dopant to a first depth of doping and the other of said second regions is doped with an n-type dopant to a second depth of doping, said first depth of doping being deeper than said second depth of doping and wherein said second region with deeper depth of doping forms a drain region of said programmable transistor and said second region with shallower depth of doping forms a source region of said programmable transistor.

Claim 45

The memory transistor as defined in claim 34 wherein the thickness of said first dielectric layer is unified so that the thickness over said channel region is equal to the thickness over said under-diffused substrate region of said first impurities.

Claim 46

The memory transistor as defined in claim 34 further comprising at least one spacer disposed alongside said first conductive gate member, said spacer is not disposed over said first region of said substrate and wherein said spacer comprising: a first portion comprised of a thermal oxide that is in contact with said first conductive gate member; and a second portion that includes a material that is not thermal oxide.

Claim 47

A non-volatile programmable semiconductor memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N memory cells organized into M horizontally directed rows and N vertically directed columns; a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell; a set of M×N floating gate structures, with each floating gate structure included in a given one of the cells in said array, with each floating gate structure comprising a thin gate oxide disposed over a channel region of a field effect transistor, said channel disposed between said source region and said drain region of said given cell, a first conductive gate member disposed over said gate oxide and having a chemically engraved surface, and said structure also comprising a second dielectric layer disposed over and conformal with said engraved surface; and a set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a first thin insulator, and oriented in a substantially horizontal direction, with at least one of said first control lines being associated with each of said rows, said associated first control line being disposed over and conformal with a corresponding said second dielectric layer to form a first capacitor with said associated first gate member within each memory cell, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said first control line in all modes of operation of said memory cell and under the operating voltage condition of said memory cell.

Claim 48

A non-volatile programmable semiconductor memory, formed on a semiconductor substrate of a first conductivity type having a major surface, said memory comprising: an array of M×N memory cells organized into M horizontally directed rows and N vertically directed columns; a set of impurity bit line regions of a second conductivity type integrally formed within said substrate, with a first impurity bit line region in a given pair of adjacent impurity bit line regions forming a drain region for a given cell and a second impurity bit line region of said given pair forming a source region for said given cell; a set of M×N floating gate structures, with each floating gate structure included in a given one of the cells in said array, with each floating gate structure comprising a thin gate oxide disposed over a channel region of a field effect transistor, said channel disposed between said source region and said drain region of said given cell, a first conductive gate member disposed over said gate oxide and having a chemically engraved surface, and said structure also comprising a second dielectric layer disposed over and conformal with said engraved surface; and a set of first control lines disposed over the major surface of the substrate, separated therefrom by a layer of a first thin insulator, and oriented in a substantially horizontal direction, with at least one of said first control lines being associated with each of said rows, said associated first control line being disposed over and conformal with a corresponding said second dielectric layer to form a first capacitor with said associated first gate member within each memory cell, thereby said second dielectric layer substantially prevents electric charge transport between said first conductive gate member and said first control line in all modes of operation of said memory cell and under the operating voltage condition of said memory cell.

Claim 49

The memory transistors of claim 41 wherein said engraved surface of said first conductive gate member is a textured polysilicon surface.

Claim 50

The memory transistors of claim 41 wherein said first thin dielectric is comprised of silicon dioxide.

Claim 51

The memory transistors of claim 41 wherein said first thin dielectric layer is capable of exhibiting electric charge transport between said first conductive gate member and said substrate.

Claim 52

The memory transistors of claim 41 further comprising at least one spacer disposed alongside said first conductive gate member and under a corresponding said first control line, and said spacer is not disposed over said channel region and wherein said spacer comprising: a first portion comprised of a thermal oxide that is in contact with said first conductive gate member; and a second portion that includes a material that is not thermal oxide.

Claim 53

The memory transistors of claim 41 wherein said second dielectric layer is characterized by the ability to exhibit a bulk-limited Frenkel-Poole type of electron conduction.

Claim 54

The memory array as defined in claim 41 wherein said first insulator layer is disposed over said bit line regions and under said first control lines to form bit line oxide; and said bit line oxide comprises a first layer of thermal oxide that is disposed under a second layer of oxide that is not a thermal oxide.

Claim 55

The memory transistors of claim 41 wherein said first conductive gate member defining an edge of at least one of said impurity bit-line regions of said substrate alongside a corresponding said first conductive gate member; and said first impurities are formed to be self-aligned with said first conductive gate member, and at least one of said first impurities forming an under-diffused substrate region under a portion of said first conductive gate member.

Claim 56

The memory transistors of claim 48 wherein one of said bit line regions of said pair is doped with an n-type dopant to a first level of doping and the other of said second bit line regions of said pair is doped with an n-type dopant to a second level of doping, said first level of doping being different from said second level of doping.

Claim 57

The memory transistor as defined in claim 48 wherein one of said bit line regions of said pair is doped with an n-type dopant to a first depth of doping and the other of said bit line regions of said pair is doped with an n-type dopant to a second depth of doping, said first depth of doping being different from said second depth of doping.

Claim 58

The memory transistors of claim 48 wherein the thickness of said gate oxide layer is unified so that the thickness over said channel region is equal to the thickness over said under-diffused substrate region of said first impurities.