Electrically erasable and electrically programmable read-only memory

Claim 1

A semiconductor memory device with a plurality of memory cells arranged in a matrix form, each of said memory cells comprising: a semiconductor region of a first conductivity type; source and drain regions of a second conductivity type, formed in said semiconductor region; a gate insulation film formed on a part of said semiconductor region between said source and drain regions; a field insulation film, formed on said semiconductor region, for separating each said memory cell from the other memory cells; an erase gate formed over said field insulation film and shared with an adjacent one of said memory cells; a floating gate formed on said gate insulation film and extending over said field insulation film, an end edge of said floating gate which is formed over said field insulation film overlapping a part of said erase gate; a first insulating film interposed between said floating gate and said erase gate; a control gate formed over said floating gate and said erase gate; a second insulating film interposed between said control gate and said floating gate; and a third insulating film interposed between said control gate and said erase gate; whereby said control gate is insulated from said erase gate and said floating gate, wherein said end edge of said floating gate overlapping said part of said erase gate is provided between said field insulation film and said control gate, and wherein said erase gate of two adjacent ones of said memory cells is commonly formed such that for the end edge of the floating gates of two adjacent ones of said plurality of memory cells both overlap said commonly formed erase gate.