In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application

Claim 1

A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, featuring a combination of process steps, such as a storage node shape, pre-clean procedure, deposition of hemispherical grain silicon, (HSG), seeds, annealing to convert said HSG silicon seeds to an HSG silicon layer, and deposition of a silicon nitride layer, all performed in situ, in a ultra high vacuum, (UHV), system, comprised the steps of: providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure; forming a storage node contact hole, in a composite insulator layer, exposing the top surface of a source region; forming a doped polysilicon plug, in said storage node contact hole; forming said storage node shape, on the top surface of said composite insulator layer, and overlying, and contacting, the top surface of said doped polysilicon plug, with native oxide forming on exposed surfaces of said storage node shape; removing a portion of said native oxide from said exposed surfaces of said storage node shape; removing remaining portion of said native oxide from said exposed surfaces of said storage node shape, in said UHV system; selectively depositing said HSG silicon seeds, on said exposed surfaces of said storage node shape, in situ, in said UHV system; performing an anneal procedure, in situ, in said UHV system, to form a DRAM storage node electrode, comprised of said HSG silicon layer, on said storage node shape, with said HSG silicon layer formed via the reaction between said HSG silicon seeds and a top portion of said storage node shape; depositing a silicon nitride layer, in situ, in said UHV system; performing an oxidation procedure, creating a nitride--oxide, capacitor dielectric layer, comprised of a silicon oxide layer, on said silicon nitride layer, with said silicon oxide layer, formed via oxidation of a top portion of said silicon nitride layer; and forming an upper plate electrode, for said capacitor structure.

Claim 2

A method of fabricating a capacitor structure, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, featuring a combination of process steps, such as a storage node shape, pre-clean procedure, deposition of hemispherical grain silicon, (HSG), seeds, annealing to convert said HSG silicon seeds to an HSG silicon layer, and deposition of a silicon nitride layer, all performed in situ, in a ultra high vacuum, (UHV), system, comprised the steps of: providing an underlying transfer gate transistor, comprised of a gate structure, on a gate insulator layer, insulator spacers on the sides of said gate structure, and a source/drain region in an area of said semiconductor substrate, not covered by said gate structure; forming a storage node contact hole, in a composite insulator layer, exposing the top surface of a source region; forming a doped polysilicon plug, in said storage node contact hole; forming said storage node shape, on the top surface of said composite insulator layer, and overlying, and contacting, the top surface of said doped polysilicon plug, with native oxide forming on exposed surfaces of said storage node shape; removing a portion of said native oxide from said exposed surfaces of said storage node shape; removing remaining portion of said native oxide from said exposed surfaces of said storage node shape, in said UHV system; selectively depositing said HSG silicon seeds, on said exposed surfaces of said storage node shape, in situ, in said UHV system; performing an anneal procedure, in situ, in said UHV system, to form a DRAM storage node electrode, comprised of said HSG silicon layer, on said storage node shape, with said HSG silicon layer formed via the reaction between said HSG silicon seeds and a top portion of said storage node shape; depositing a silicon nitride layer, in situ, in said UHV system; performing an oxidation procedure, creating a nitride--oxide, capacitor dielectric layer, comprised of a silicon oxide layer, on said silicon nitride layer, with said silicon oxide layer, formed via oxidation of a top portion of said silicon nitride layer; and forming an upper plate electrode, for said capacitor structure.

Claim 11

A method of fabricating a DRAM capacitor structure, on a semiconductor substrate, in which a combination of process steps, featuring a high vacuum pre-clean of a storage node shape, deposition of hemispherical grain, (HSG), silicon seeds, an anneal cycle used to form a HSG silicon layer, and a silicon nitride deposition, are all performed in situ, in an ultra high vacuum, (UHV), system, is used to form a storage node structure for said DRAM capacitor structure, comprising the steps of: providing an underlying transfer gate transistor, on said semiconductor substrate, comprised of a polysilicon gate structure, with insulator spacers on the sides of said polysilicon gate structure, overlying a silicon dioxide gate insulator layer, and a source/drain region, in an area of said semiconductor substrate, not covered by said gate structure; depositing a composite insulator layer; forming a storage node contact hole in said composite insulator layer, exposing the top surface of the source region, of said source/drain region; depositing a doped polysilicon layer, completely filling said storage node contact hole; removing said doped polysilicon layer, from the top surface of said composite insulator layer, forming a doped polysilicon plug, in said storage node contact hole; depositing an amorphous silicon layer; patterning of said amorphous silicon layer to form an amorphous silicon, storage node shape, overlying, and contacting, the top surface of said doped polysilicon plug, located in said storage node contact hole, with native oxide forming on exposed surfaces of said amorphous silicon, storage node shape; performing a first pre-clean procedure, in a DHF solution, to remove a first portion of said native oxide from said exposed surfaces of said amorphous silicon, storage node shape; performing a second pre-clean procedure, in said UHV system, at a pressure below 1E-8 torr, to remove any remaining portions of said native oxide from said exposed surfaces of said amorphous silicon, storage node shape; selectively depositing said HSG silicon seeds, in situ, in said UHV system, on said exposed surfaces of said amorphous silicon, storage node shape; performing an anneal procedure, in situ, in said UHV system, forming a DRAM storage node electrode, comprised of said HSG silicon layer, on said amorphous silicon, storage node shape, with said HSG silicon layer, formed during said anneal procedure, via the reaction between said HSG silicon seeds, with the top portion of said amorphous silicon, storage node shape; depositing said silicon nitride layer, in situ, in said UHV system; oxidizing the top surface of said silicon nitride layer, to create a capacitor dielectric layer, comprised of a silicon oxide layer, on the unoxidized portion of said silicon nitride layer; depositing a polysilicon layer; and patterning of said polysilicon layer to form a polysilicon upper electrode, for said DRAM capacitor structure.

Claim 12

A method of fabricating a DRAM capacitor structure, on a semiconductor substrate, in which a combination of process steps, featuring a high vacuum pre-clean of a storage node shape, deposition of hemispherical grain, (HSG), silicon seeds, an anneal cycle used to form a HSG silicon layer, and a silicon nitride deposition, are all performed in situ, in an ultra high vacuum, (UHV), system, is used to form a storage node structure for said DRAM capacitor structure, comprising the steps of: providing an underlying transfer gate transistor, on said semiconductor substrate, comprised of a polysilicon gate structure, with insulator spacers on the sides of said polysilicon gate structure, overlying a silicon dioxide gate insulator layer, and a source/drain region, in an area of said semiconductor substrate, not covered by said gate structure; depositing a composite insulator layer; forming a storage node contact hole in said composite insulator layer, exposing the top surface of the source region, of said source/drain region; depositing a doped polysilicon layer, completely filling said storage node contact hole; removing said doped polysilicon layer, from the top surface of said composite insulator layer, forming a doped polysilicon plug, in said storage node contact hole; depositing an amorphous silicon layer; patterning of said amorphous silicon layer to form an amorphous silicon, storage node shape, overlying, and contacting, the top surface of said doped polysilicon plug, located in said storage node contact hole, with native oxide forming on exposed surfaces of said amorphous silicon, storage node shape; performing a first pre-clean procedure, in a DHF solution, to remove a first portion of said native oxide from said exposed surfaces of said amorphous silicon, storage node shape; performing a second pre-clean procedure, in said UHV system, at a pressure below 1E-8 torr, to remove any remaining portions of said native oxide from said exposed surfaces of said amorphous silicon, storage node shape; selectively depositing said HSG silicon seeds, in situ, in said UHV system, on said exposed surfaces of said amorphous silicon, storage node shape; performing an anneal procedure, in situ, in said UHV system, forming a DRAM storage node electrode, comprised of said HSG silicon layer, on said amorphous silicon, storage node shape, with said HSG silicon layer, formed during said anneal procedure, via the reaction between said HSG silicon seeds, with the top portion of said amorphous silicon, storage node shape; depositing said silicon nitride layer, in situ, in said UHV system; oxidizing the top surface of said silicon nitride layer, to create a capacitor dielectric layer, comprised of a silicon oxide layer, on the unoxidized portion of said silicon nitride layer; depositing a polysilicon layer; and patterning of said polysilicon layer to form a polysilicon upper electrode, for said DRAM capacitor structure.