Method to increase capacitance of a DRAM cell

Claim 1

A method for creating a storage node electrode, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising the steps of: providing a transfer gate transistor, comprised of a gate structure, on a gate insulator layer, and with a source/drain region, located in a region of said semiconductor substrate, not covered by said gate structure; forming a storage node contact hole, in an insulator layer, exposing a source region, of said source/drain region; forming a polysilicon plug structure, in said storage node contact hole; depositing a first polysilicon layer; depositing a second polysilicon layer, on said first polysilicon layer; depositing an amorphous silicon layer on said second polysilicon layer; annealing of said amorphous silicon layer, converting said amorphous silicon layer to a hemispherical grain, (HSG), silicon layer; and patterning of said HSG silicon layer, of said second polysilicon layer, and of said first polysilicon layer, to form said storage node electrode.

Claim 2

A method for creating a storage node electrode, for a dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising the steps of: providing a transfer gate transistor, comprised of a gate structure, on a gate insulator layer, and with a source/drain region, located in a region of said semiconductor substrate, not covered by said gate structure; forming a storage node contact hole, in an insulator layer, exposing a source region, of said source/drain region; forming a polysilicon plug structure, in said storage node contact hole; depositing a first polysilicon layer; depositing a second polysilicon layer, on said first polysilicon layer; depositing an amorphous silicon layer on said second polysilicon layer; annealing of said amorphous silicon layer, converting said amorphous silicon layer to a hemispherical grain, (HSG), silicon layer; and patterning of said HSG silicon layer, of said second polysilicon layer, and of said first polysilicon layer, to form said storage node electrode.

Claim 9

A method for fabricating a stacked capacitor structure, for a DRAM device, on a semiconductor substrate, wherein the surface area of the stacked capacitor structure is increased via the use of an HSG silicon layer, functioning as the top layer of a storage node electrode, comprising the steps of: providing a transfer gate transistor, comprised of a gate structure on a gate insulator layer, and with a source/drain region, in an area of said semiconductor substrate not covered by said gate structure; depositing an insulator layer; planarizing said insulator layer; opening a storage node contact hole in said insulator layer, exposing the top surface of a source region, of said source/drain region; forming a polysilicon plug structure in said storage node contact hole; depositing an undoped polysilicon layer, in a low pressure chemical vapor deposition, (LPCVD), furnace; using said LPCVD furnace, in situ depositing a doped polysilicon layer on said undoped polysilicon layer; using said LPCVD furnace, depositing an amorphous silicon layer on said doped polysilicon layer; using said LPCVD furnace, in situ annealing to convert said amorphous silicon layer to a hemispherical grain, (HSG), silicon layer; patterning of said HSG silicon layer, of said doped polysilicon layer, and of said undoped polysilicon layer, to create said storage node electrode; forming a capacitor dielectric layer on said storage node electrode; and forming a polysilicon upper electrode, for said stacked capacitor structure, overlying said capacitor dielectric layer, and overlying said storage node structure.

Claim 10

A method for fabricating a stacked capacitor structure, for a DRAM device, on a semiconductor substrate, wherein the surface area of the stacked capacitor structure is increased via the use of an HSG silicon layer, functioning as the top layer of a storage node electrode, comprising the steps of: providing a transfer gate transistor, comprised of a gate structure on a gate insulator layer, and with a source/drain region, in an area of said semiconductor substrate not covered by said gate structure; depositing an insulator layer; planarizing said insulator layer; opening a storage node contact hole in said insulator layer, exposing the top surface of a source region, of said source/drain region; forming a polysilicon plug structure in said storage node contact hole; depositing an undoped polysilicon layer, in a low pressure chemical vapor deposition, (LPCVD), furnace; using said LPCVD furnace, in situ depositing a doped polysilicon layer on said undoped polysilicon layer; using said LPCVD furnace, depositing an amorphous silicon layer on said doped polysilicon layer; using said LPCVD furnace, in situ annealing to convert said amorphous silicon layer to a hemispherical grain, (HSG), silicon layer; patterning of said HSG silicon layer, of said doped polysilicon layer, and of said undoped polysilicon layer, to create said storage node electrode; forming a capacitor dielectric layer on said storage node electrode; and forming a polysilicon upper electrode, for said stacked capacitor structure, overlying said capacitor dielectric layer, and overlying said storage node structure.