US5583070A
Expired / Lapsed
US
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Process to form rugged polycrystalline silicon surfaces
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-07-07
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Granted: 1996-12-10
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Expires: 2015-07-07
Abstract
Abstract A process for fabricating stacked capacitor, DRAM, devices, has been developed in which the surface area of the storage node has been significantly increased as a result of a unique set of deposition and annealing conditions. An amorphous polysilicon layer, used as the upper layer of the storage node, is ramped up in pure nitrogen, and then insitu annealed, to result in a polycrystalline structure, exhibiting significant surface area increases, due to the formation of surface concave and convex protrusions. The increase in storage node surface area allows for increased DRAM capacitance, without the use of larger dimension stacked capacitors, or thinner dielectrics.
Inventors
- 👤 Chih-Cherng Liao
- 👤 Haw Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:31
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10P; H10P50/00; Y; Y10; Y10S; Y10S148/00; Y10S148/014; Y10S438/00; Y10S438/954; Y10S438/964
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
310 words
A method for fabricating stacked capacitor, dynamic random access memory, (DRAM), devices on a semiconductor substrate, comprising the steps of: providing a transfers gate transistor, with a first N type doped region, and a second N type doped region, in said semiconductor substrate; depositing a first insulator layer on said transfer gate transistor, including deposition on said first N type doped region and on said second N type doped region; opening a first contact hole, in said first insulator layer, to expose said first N type doped region, in said transfer gate transistor; depositing an undoped, first polysilicon layer on said transfer gate transistor, contacting said first N type doped region, in said first contact hole; depositing an insitu doped, second polysilicon layer on said first polysilicon layer; depositing a third polysilicon layer on said doped, second polysilicon layer; insitu annealing of said third polysilicon layer, to increase surface roughness of said third polysilicon layer; patterning of said first polysilicon layer, said doped, second polysilicon layer, and said third polysilicon layer, to form lower electrode structure; forming a composite dielectric layer on surface of said third polysilicon layer, and on said transfer gate transistor, not covered by said lower electrode structure; depositing a fourth polysilicon layer on said composite dielectric layer; patterning of said fourth polysilicon layer, to form upper electrode structure; depositing a second insulator layer on said upper electrode structure, and on said transfer gate transistor, not covered by said upper electrode structure; opening a second contact hole, in said second insulator layer, to expose said second N type doped region, in said transfer gate transistor; depositing a metal layer on said upper electrode structure, and on said transfer gate transistor, and contacting said second N type region, in said second contact hole; and patterning said metal layer to form metal contact to said second N type region.
Claim 2
Independent Claim
310 words
A method for fabricating stacked capacitor, dynamic random access memory, (DRAM), devices on a semiconductor substrate, comprising the steps of: providing a transfers gate transistor, with a first N type doped region, and a second N type doped region, in said semiconductor substrate; depositing a first insulator layer on said transfer gate transistor, including deposition on said first N type doped region and on said second N type doped region; opening a first contact hole, in said first insulator layer, to expose said first N type doped region, in said transfer gate transistor; depositing an undoped, first polysilicon layer on said transfer gate transistor, contacting said first N type doped region, in said first contact hole; depositing an insitu doped, second polysilicon layer on said first polysilicon layer; depositing a third polysilicon layer on said doped, second polysilicon layer; insitu annealing of said third polysilicon layer, to increase surface roughness of said third polysilicon layer; patterning of said first polysilicon layer, said doped, second polysilicon layer, and said third polysilicon layer, to form lower electrode structure; forming a composite dielectric layer on surface of said third polysilicon layer, and on said transfer gate transistor, not covered by said lower electrode structure; depositing a fourth polysilicon layer on said composite dielectric layer; patterning of said fourth polysilicon layer, to form upper electrode structure; depositing a second insulator layer on said upper electrode structure, and on said transfer gate transistor, not covered by said upper electrode structure; opening a second contact hole, in said second insulator layer, to expose said second N type doped region, in said transfer gate transistor; depositing a metal layer on said upper electrode structure, and on said transfer gate transistor, and contacting said second N type region, in said second contact hole; and patterning said metal layer to form metal contact to said second N type region.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein said transfer gate transistor is an N type, field effect transistor, with a silicon dioxide gate insulator of between about 100 to 300 Angstroms.
Claim 4
Dependent Claim
36 words
The method of claim 1, wherein said first polysilicon layer, is deposited intrinsically using LPCVD processing, at a temperature between about 580° to 650° C., to a thickness between about 1500 to 2500 Angstroms, using SiH4.
Claim 5
Dependent Claim
59 words
The method of claim 1, wherein said doped, second polysilicon layer is deposited using an LPCVD, insitu doping, process, at a temperature between about 530° to 600° C., to a thickness between about 1500 to 4000 Angstroms, using a flow between about 1000 to 1500 sccm of SiH4, and a flow between about 100 to 300 sccm of PH3.
Claim 6
Dependent Claim
45 words
The method of claim 1, wherein said third polysilicon layer is deposited intrinsically, using LPCVD processing, at a temperature between about 510° to 600° C., to a thickness between about 500 to 1500 Angstroms, using SiH4, at a pressure between about 0.15 to 0.25 Torr.
Claim 7
Dependent Claim
33 words
The method of claim 1, wherein said insitu annealing is performed, in an LPCVD system, at a temperature between about 530° to 600° C., at a pressure between about 0.2 to 1.0 Torr.
Claim 8
Dependent Claim
26 words
The method of claim 1, wherein surface area of said third polysilicon layer is increased by 40 to 80%, as a result of said insitu anneal.
Claim 9
Dependent Claim
100 words
The method of claim 1, wherein said composite dielectric layer is composed of silicon oxynitride - silicon nitride - silicon dioxide, obtained by: native oxide growth on said third polysilicon layer, to a thickness between about 10 to 20 Angstroms; deposition of a silicon nitride layer, using LPCVD processing, at a temperature between about 650° to 750° C., to a thickness between about 40 to 80 Angstroms; and an oxidation of said silicon nitride layer, at a temperature between about 850° to 900° C., in an oxygen -steam ambient, to form between about 10 to 30 Angstroms of silicon oxynitride.
Claim 10
Dependent Claim
57 words
The method of claim 1, wherein said fourth polysilicon layer is deposited using an LPCVD, insitu doping process, at a temperature between about 580° C. to 650° C., to a thickness between about 750 to 2500 Angstroms, using a SiH4 flow between about 1000 to 1500 sccm, and a PH3 flow between about 100 to 300 sccm.
Claim 11
Independent Claim
350 words
A method for fabricating stacked capacitor, dynamic random access memory, (DRAM), devices, on a semiconductor substrate, comprising the steps of: providing a transfer gate transistor, with a first N type source and drain region, and a second N type source and drain region, in said semiconductor substrate; depositing a first insulator layer on said transfer gate transistor, including deposition on said first N type source and drain region and on said second N type source and drain region; opening a first contact hole, in said first insulator layer, to expose said first N type source and drain region, in said transfer gate transistor; depositing an undoped first polysilicon layer on said transfer gate transistor, contacting said first N type source and drain region, in said first contact hole; depositing an insitu doped, second polysilicon layer on said first polysilicon layer; depositing an amorphous, third polysilicon layer on said doped, second polysilicon layer; insitu annealing of said amorphous, third polysilicon layer, to convert said amorphous, third polysilicon layer, to a roughened surface, third polysilicon layer; patterning of said first polysilicon layer, said doped, second polysilicon layer, and said roughened surface, third polysilicon layer, to form storage node structure, of said stacked capacitor structure; forming a composite dielectric layer, on said roughened surface, third polysilicon layer, and on said transfer gate transistor, not covered by said storage node structure; depositing a fourth polysilicon layer on said composite dielectric layer; patterning of said fourth polysilicon layer, to form cell plate structure, of said stacked capacitor structure; depositing a second insulator layer on said cell plate structure, and on said transfer gate transistor, not covered by said stacked capacitor structure; opening a second contact hole, in said second insulator layer, to expose said second N type source and drain region, in said transfer gate transistor; depositing a metal layer on said cell plate structure, and on said transfer gate transistor, and contacting said second N type source and drain region, in said second contact hole; and patterning of said metal layer to form metal contact to said second N type source and drain region.
Claim 12
Independent Claim
350 words
A method for fabricating stacked capacitor, dynamic random access memory, (DRAM), devices, on a semiconductor substrate, comprising the steps of: providing a transfer gate transistor, with a first N type source and drain region, and a second N type source and drain region, in said semiconductor substrate; depositing a first insulator layer on said transfer gate transistor, including deposition on said first N type source and drain region and on said second N type source and drain region; opening a first contact hole, in said first insulator layer, to expose said first N type source and drain region, in said transfer gate transistor; depositing an undoped first polysilicon layer on said transfer gate transistor, contacting said first N type source and drain region, in said first contact hole; depositing an insitu doped, second polysilicon layer on said first polysilicon layer; depositing an amorphous, third polysilicon layer on said doped, second polysilicon layer; insitu annealing of said amorphous, third polysilicon layer, to convert said amorphous, third polysilicon layer, to a roughened surface, third polysilicon layer; patterning of said first polysilicon layer, said doped, second polysilicon layer, and said roughened surface, third polysilicon layer, to form storage node structure, of said stacked capacitor structure; forming a composite dielectric layer, on said roughened surface, third polysilicon layer, and on said transfer gate transistor, not covered by said storage node structure; depositing a fourth polysilicon layer on said composite dielectric layer; patterning of said fourth polysilicon layer, to form cell plate structure, of said stacked capacitor structure; depositing a second insulator layer on said cell plate structure, and on said transfer gate transistor, not covered by said stacked capacitor structure; opening a second contact hole, in said second insulator layer, to expose said second N type source and drain region, in said transfer gate transistor; depositing a metal layer on said cell plate structure, and on said transfer gate transistor, and contacting said second N type source and drain region, in said second contact hole; and patterning of said metal layer to form metal contact to said second N type source and drain region.
Claim 13
Dependent Claim
30 words
The method of claim 10, wherein said transfer gate transistor is an N type, field effect transistor, with a silicon dioxide gate insulator of between about 100 to 300 Angstroms.
Claim 14
Dependent Claim
36 words
The method of claim 10, wherein said first polysilicon layer is deposited intrinsically, using LPCVD processing, at a temperature between about 580° to 650° C., to a thickness between about 1500 to 2500 Angstroms, using SiH4.
Claim 15
Dependent Claim
59 words
The method of claim 10, wherein said doped second polysilicon layer is deposited using an LPCVD, insitu doped, process, at a temperature between about 530 to 600° C., to a thickness between about 1500 to 4000 Angstroms, using a flow between about 1000 to 1500 sccm of SiH4, and a flow between about 100 to 300 sccm of PH3.
Claim 16
Dependent Claim
46 words
The method of claim 10, wherein said amorphous, third polysilicon layer is deposited intrinsically, using LPCVD processing at a temperature between about 510° to 600° C., to a thickness between about 500 to 1500 Angstroms, using SiH4, at a pressure between about 0.15 to 0.25 Torr.
Claim 17
Dependent Claim
39 words
The method of claim 10, wherein said insitu annealing, of said amorphous, third polysilicon layer is performed, in an LPCVD system, at a temperature between about 530° to 600° C., at a pressure between about 0.2 to 1.0 Torr.
Claim 18
Dependent Claim
40 words
The method of claim 10, wherein surface area of said roughened surface, third polysilicon layer, is increased by between about 40 to 80%, as a result of conversion from said amorphous, third polysilicon layer, via use of said insitu annealing.
Claim 19
Dependent Claim
101 words
The method of claim 10, wherein said composite dielectric layer is composed of silicon oxynitride - silicon nitride - silicon dioxide, obtained by: native oxide growth on said toughened surface, third polysilicon layer, to a thickness between about 10 to 20 Angstroms; deposition of a silicon nitride layer, using LPCVD processing, at a temperature between about 650° to 750° C., to a thickness between about 40 to 80 Angstroms; and an oxidation of said silicon nitride layer, at a temperature between about 850° to 950° C., in an oxygen--steam ambient, to form between about 10 to 30 Angstroms of silicon oxynitride.
Claim 20
Dependent Claim
56 words
The method of claim 10, wherein said fourth polysilicon layer is deposited using an LPCVD, insitu doped, process, at a temperature between about 580° to 650° C., to a thickness between about 750 to 2500 Angstroms, using a SiH4 flow between about 1000 to 1500 sccm, and a PH3 flow between about 100 to 300 sccm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |