Process for fabricating bottom electrode of capacitor

Claim 1

A process for fabricating bottom electrodes for storage capacitors of memory cell units of a dynamic random-access memory device, the process comprising the steps of: providing a semiconductor substrate; forming a first dielectric layer covering the surface of the substrate; forming a silicon nitride layer covering the first dielectric layer; patterning and etching the silicon nitride layer in a photolithographic procedure to form contact openings revealing the surface of the substrate; forming an electrically conductive layer covering the silicon nitride layer and filling into the contact opening thereby contacting the exposed regions of the substrate in the openings; forming a first hemispherical-grain polysilicon layer covering the conductive layer; forming a second dielectric layer covering the first hemispherical-grain polysilicon layer; patterning and etching in a photolithographic procedure to etch into the second dielectric layer, the first hemispherical-grain polysilicon layer and the conductive layer, thereby exposing the surface of the silicon nitride layer; forming a second hemispherical-grain polysilicon layer covering the exposed surface of the conductive layer, the second dielectric layer and the silicon nitride layer; removing the second hemispherical-grain polysilicon layer covering the surface of the silicon nitride layer and the second dielectric layer, thereby exposing the surface of the silicon nitride layer and the second dielectric layer; and removing the second dielectric layer thereby exposing the surface of the first hemispherical-grain polysilicon layer, wherein the first hemispherical-grain polysilicon layer is utilized as the bottom electrode for the storage capacitor.