US5866455A
Expired / Lapsed
US
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Method for forming a dram cell with a multiple pillar-shaped capacitor
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-10-20
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Granted: 1999-02-02
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Expires: 2017-10-20
Abstract
Abstract A method for forming a multiple pillar-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes patterning to form a doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the doped polysilicon layer communicates to the substrate. Next, a titanium nitride layer (122) is conformably formed on the doped polysiliocn layer, and a hemispherical grained silicon layer (124) is then formed on the titanium nitride layer, wherein the titanium nitride layer serves as a seed layer for forming the hemispherical grained silicon layer. The present invention also includes etching the titanium nitride layer using the hemispherical grained silicon layer as a mask, and etching portions of the doped polysilicon layer using the titanium nitride layer as an etch mask. Finally, a dielectric layer (136) is formed on the doped polysilicon layer, and a conductive layer (138) is then formed on the dielectric layer.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
126 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: patterning to form a doped polysilicon layer over a semiconductor substrate, at least a portion of said doped polysilicon layer communicating to said substrate; conformably forming a titanium nitride layer on said doped polysilicon layer; forming a hemispherical grained silicon layer on said titanium nitride layer, said titanium nitride layer serving as a seed layer for forming said hemispherical grained silicon layer; etching said titanium nitride layer using said hemispherical grained silicon layer as a mask; etching portions of said doped polysilicon layer using said titanium nitride layer as an etch mask; forming a dielectric layer on said doped polysilicon layer; and forming a conductive layer on said dielectric layer.
Claim 2
Independent Claim
126 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: patterning to form a doped polysilicon layer over a semiconductor substrate, at least a portion of said doped polysilicon layer communicating to said substrate; conformably forming a titanium nitride layer on said doped polysilicon layer; forming a hemispherical grained silicon layer on said titanium nitride layer, said titanium nitride layer serving as a seed layer for forming said hemispherical grained silicon layer; etching said titanium nitride layer using said hemispherical grained silicon layer as a mask; etching portions of said doped polysilicon layer using said titanium nitride layer as an etch mask; forming a dielectric layer on said doped polysilicon layer; and forming a conductive layer on said dielectric layer.
Claim 3
Dependent Claim
32 words
The method according to claim 1, before forming said doped polysilicon layer, further comprising forming a stack of a first silicon oxide layer and a second silicon oxide layer on said substrate.
Claim 4
Dependent Claim
48 words
The method according to claim 2, wherein said stack of the first silicon oxide layer and the second silicon oxide layer has a contact hole formed therein so that said at least a portion of the doped polysilicon layer is communicated to said substrate via the contact hole.
Claim 5
Dependent Claim
15 words
The method according to claim 3, wherein said first silicon oxide layer comprises tetraethylorthosilicate (TEOS).
Claim 6
Dependent Claim
16 words
The method according to claim 3, wherein said first silicon oxide layer comprises boro-phosphosilicate glass (BPSG).
Claim 7
Dependent Claim
20 words
The method according to claim 1, wherein said titanium nitride layer is formed using low pressure chemical vapor deposition process.
Claim 8
Dependent Claim
22 words
The method according to claim 1, wherein said hemispherical grained silicon layer is formed using plasma enhanced chemical vapor deposition (PECVD) process.
Claim 9
Dependent Claim
21 words
The method according to claim 7, wherein said hemispherical grained silicon layer is formed at a temperature of about 300° C.
Claim 10
Independent Claim
173 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; forming a silicon oxide layer on said first dielectric layer; patterning said first dielectric layer and said silicon oxide layer to form a contact hole in said first dielectric layer and said silicon oxide layer, therefore exposing a portion of the substrate; patterning to form a doped polysilicon layer on said silicon oxide layer; conformably forming a titanium nitride layer on said doped polysiliocn layer; forming a hemispherical grained silicon layer on said titanium nitride layer, said titanium nitride layer serving as a seed layer for forming said hemispherical grained silicon layer; etching said titanium nitride layer using said hemispherical grained silicon layer as a mask; removing said hemispherical grained silicon layer; etching portions of said doped polysilicon layer using said titanium nitride layer as an etch mask; forming a second dielectric layer on said doped polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 11
Independent Claim
173 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; forming a silicon oxide layer on said first dielectric layer; patterning said first dielectric layer and said silicon oxide layer to form a contact hole in said first dielectric layer and said silicon oxide layer, therefore exposing a portion of the substrate; patterning to form a doped polysilicon layer on said silicon oxide layer; conformably forming a titanium nitride layer on said doped polysiliocn layer; forming a hemispherical grained silicon layer on said titanium nitride layer, said titanium nitride layer serving as a seed layer for forming said hemispherical grained silicon layer; etching said titanium nitride layer using said hemispherical grained silicon layer as a mask; removing said hemispherical grained silicon layer; etching portions of said doped polysilicon layer using said titanium nitride layer as an etch mask; forming a second dielectric layer on said doped polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 12
Dependent Claim
14 words
The method according to claim 9, wherein said first dielectric layer comprises tetraethylorthosilicate (TEOS).
Claim 13
Dependent Claim
15 words
The method according to claim 9, wherein said first dielectric layer comprises boro-phosphosilicate glass (BPSG).
Claim 14
Dependent Claim
20 words
The method according to claim 9, wherein said titanium nitride layer is formed using low pressure chemical vapor deposition process.
Claim 15
Dependent Claim
22 words
The method according to claim 9, wherein said hemispherical grained silicon layer is formed using plasma enhanced chemical vapor deposition (PECVD) process.
Claim 16
Dependent Claim
21 words
The method according to claim 13, wherein said hemispherical grained silicon layer is formed at a temperature of about 300° C.
References Cited (Backward Citations)
US5726085A
Cited
US5754390A
Cited
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