Method of fabricating a dynamic random access memory (DRAM) cell capacitor using hemispherical grain (HSG) polysilicon and selective polysilicon etchback

Claim 1

A method for forming a storage node of a capacitor having increased charge storage capacity, comprising the steps of: a. forming a doped polysilicon region; b. depositing a thin layer of hemipherical grain polysilicon having a grain size and film thickness on the same order of magnitude on said doped polysilicon region; and c. without masking said thin layer of hemispherical grain polysilicon, etching said doped polysilicon region and said thin layer of hemispherical grain polysilicon using an etch chemistry that etches said doped polysilicon region faster than said thin layer of hemispherical grain polysilicon to increase an upper surface area of said storage node wherein said etching step continues until all of said hemispherical grain polysilicon is removed from said upper surface of said storage node.

Claim 2

A method for forming a storage node of a capacitor having increased charge storage capacity, comprising the steps of: a. forming a doped polysilicon region; b. depositing a thin layer of hemipherical grain polysilicon having a grain size and film thickness on the same order of magnitude on said doped polysilicon region; and c. without masking said thin layer of hemispherical grain polysilicon, etching said doped polysilicon region and said thin layer of hemispherical grain polysilicon using an etch chemistry that etches said doped polysilicon region faster than said thin layer of hemispherical grain polysilicon to increase an upper surface area of said storage node wherein said etching step continues until all of said hemispherical grain polysilicon is removed from said upper surface of said storage node.

Claim 11

A method of forming a memory cell, comprising the steps of: a. forming an active area in a semiconductor body; b. forming a polysilicon gate extending over said active area; c. forming a bitline over and insulated from said polysilicon gate, said bitline being electrically coupled to said active area on a first side of said polysilicon gate; and d. forming a first electrode electrically coupled to said active area on a second side of said polysilicon gate by: i. forming a doped polysilicon node having sidewalls and an upper surface; ii. depositing a thin layer of undoped hemispherical grain polysilicon having a grain size and film thickness on the same order of magnitude on said sidewalls and said upper surface of said doped polysilicon node; and iii. without masking said thin layer of hemispherical grain polysilicon etching said doped polysilicon node and said thin layer of hemispherical grain polysilicon with an etch chemistry having a selectivity of at least 3:1 between the doped polysilicon node and the thin layer of undoped hemispherical grain polysilicon, wherein said etching step continues until all of said hemispherical grain polysilicon is removed from said upper surface of said doped polysilicon node; e. forming a capacitor dielectric over said first electrode; and f. forming a second electrode over said capacitor dielectric such that said first electrode, said capacitor dielectric and said second dielectric form a capacitor.

Claim 12

A method of forming a memory cell, comprising the steps of: a. forming an active area in a semiconductor body; b. forming a polysilicon gate extending over said active area; c. forming a bitline over and insulated from said polysilicon gate, said bitline being electrically coupled to said active area on a first side of said polysilicon gate; and d. forming a first electrode electrically coupled to said active area on a second side of said polysilicon gate by: i. forming a doped polysilicon node having sidewalls and an upper surface; ii. depositing a thin layer of undoped hemispherical grain polysilicon having a grain size and film thickness on the same order of magnitude on said sidewalls and said upper surface of said doped polysilicon node; and iii. without masking said thin layer of hemispherical grain polysilicon etching said doped polysilicon node and said thin layer of hemispherical grain polysilicon with an etch chemistry having a selectivity of at least 3:1 between the doped polysilicon node and the thin layer of undoped hemispherical grain polysilicon, wherein said etching step continues until all of said hemispherical grain polysilicon is removed from said upper surface of said doped polysilicon node; e. forming a capacitor dielectric over said first electrode; and f. forming a second electrode over said capacitor dielectric such that said first electrode, said capacitor dielectric and said second dielectric form a capacitor.