US5899716A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Oxygen ion implantation procedure to increase the surface area of an STC structure
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1997-05-19
•
Granted: 1999-05-04
•
Expires: 2017-05-19
Abstract
Abstract A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, with increased surface area, resulting from the formation of protruding polysilicon shapes. The protruding polysilicon shapes are obtained using dielectric regions as a mask during a selective, anisotropic RIE procedure, used to define the storage node electrode shape. The dielectric regions are created via oxygen ion implantation into exposed regions of a polysilicon layer. An anneal is used to convert the oxygen implanted polysilicon regions, to dielectric regions.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:29
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
221 words
A method of fabricating a dynamic random access memory, (DRAMA), device, on a semiconductor substrate, featuring a stacked capacitor (STC), structure overlying a transfer gate transistor, and with said STC structure comprised of a storage node electrode, with protruding polysilicon shapes, a capacitor dielectric layer, and an overlying upper electrode; comprising the steps of: providing said transfer gate transistor; depositing an insulator layer on said transfer gate transistor; forming a storage node contact hole in said insulator layer, exposing a source and drain region of said transfer gate transistor; forming a first polysilicon shape, completely filling said storage node contact hole, with a shallow trench located in the center of said first polysilicon shape; selectively forming a dielectric layer on portions of said first polysilicon shape, via an oxygen ion implantation procedure, and anneal procedure; forming the storage node electrode, of said STC structure, via selective etching of the regions of said first polysilicon shape, not covered by said dielectric layer, with said storage node electrode comprised with protruding polysilicon shapes, overlying a wider, flat, bottom polysilicon shape, which in turn contacts said source and drain region, exposed in said storage node contact; forming said capacitor dielectric layer, of said STC structure, on said storage node electrode; and forming said upper electrode, of said STC structure, on said capacitor dielectric layer.
Claim 2
Independent Claim
221 words
A method of fabricating a dynamic random access memory, (DRAMA), device, on a semiconductor substrate, featuring a stacked capacitor (STC), structure overlying a transfer gate transistor, and with said STC structure comprised of a storage node electrode, with protruding polysilicon shapes, a capacitor dielectric layer, and an overlying upper electrode; comprising the steps of: providing said transfer gate transistor; depositing an insulator layer on said transfer gate transistor; forming a storage node contact hole in said insulator layer, exposing a source and drain region of said transfer gate transistor; forming a first polysilicon shape, completely filling said storage node contact hole, with a shallow trench located in the center of said first polysilicon shape; selectively forming a dielectric layer on portions of said first polysilicon shape, via an oxygen ion implantation procedure, and anneal procedure; forming the storage node electrode, of said STC structure, via selective etching of the regions of said first polysilicon shape, not covered by said dielectric layer, with said storage node electrode comprised with protruding polysilicon shapes, overlying a wider, flat, bottom polysilicon shape, which in turn contacts said source and drain region, exposed in said storage node contact; forming said capacitor dielectric layer, of said STC structure, on said storage node electrode; and forming said upper electrode, of said STC structure, on said capacitor dielectric layer.
Claim 3
Dependent Claim
42 words
The method of claim 1, wherein said transfer gate transistor is an N channel metal oxide semiconductor field effect transistor, (MOSFET), with a silicon dioxide gate insulator layer, a polysilicon gate structure, insulator sidewall spacers, and N type source and drain regions.
Claim 4
Dependent Claim
36 words
The method of claim 1, wherein said transfer gate transistor is a P channel MOSFET, with a silicon dioxide gate insulator layer, a polysilicon gate structure, insulator sidewall spacers, and P type source and drain regions.
Claim 5
Dependent Claim
62 words
The method of claim 1, wherein said storage node contact hole is formed, via anisotropic reactive ion etch, (RIE), procedures, using CHF 3 as an etchant, in a composite insulator layer, comprised of an overlying boro-phosphosilicate, (BPSG), layer, at a thickness between about 3000 to 8000 Angstroms, and an underlying silicon oxide layer, at a thickness between about 1000 to 2000 Angstroms.
Claim 6
Dependent Claim
49 words
The method of claim 1, wherein said storage node electrode, of said STC structure, is formed from a a polysilicon layer, obtained via N type, in situ doping, low pressure chemical vapor deposition, (LPCVD), procedures, with a N type surface concentration between about 1E20 to 1E21 atoms/cm 3 .
Claim 7
Dependent Claim
28 words
The method of claim 1, wherein said storage node electrode, of said STC structure, is comprised of said protruding polysilicon shapes, on said underlying, wider, flat polysilicon shape.
Claim 8
Dependent Claim
41 words
The method of claim 1, wherein said protruding polysilicon shapes are formed by patterning of a polysilicon layer, via a selective, anisotropic RIE procedure, using HBr--SF 6 --Cl 2 as an etchant, and using a overlying dielectric shape as a mask.
Claim 9
Dependent Claim
45 words
The method of claim 7, wherein said dielectric shape, used as a mask to define said protruding polysilicon shapes, is obtained via said oxygen ion implantation procedure, using a zero degree implantation angle, followed by an anneal, in a nitrogen, or in an argon ambient.
Claim 10
Dependent Claim
87 words
The method of claim 1, wherein said capacitor dielectric layer is composed of silicon oxynitride silicon--nitride--silicon oxide, (ONO), obtained by thermal oxidation of a top surface of said storage node electrode, to form a silicon oxide layer, between about 10 to 50 Angstroms, followed by a deposition of silicon nitride, to a thickness between about 10 to 20 Angstroms, and thermal oxidation of a top portion of said silicon nitride layer, creating a silicon oxynitride layer, on the unoxidized silicon nitride layer, overlying said silicon oxide layer.
Claim 11
Dependent Claim
45 words
The method of claim 1, wherein said upper electrode, of said STC structure, is a doped polysilicon structure, formed from a LPCVD polysilicon layer, at a thickness between about 1000 to 3000 Angstroms, and patterned using anisotropic RIE procedures, using Cl 2 as an etchant.
Claim 12
Independent Claim
276 words
A method for fabricating a stacked capacitor structure, (STC), overlying a transfer gate transistor structure, for a DRAM device, in which a surface area of a storage node electrode is increased by formation of protruding polysilicon shapes, comprising the steps of: depositing an interlevel composite insulator layer on said transfer gate transistor; opening a storage node contact hole in said interlevel composite insulator layer, exposing a source and drain region, in a bottom of said storage node contact hole; depositing a polysilicon layer on a top surface of said interlevel composite insulator layer, and completely filling said storage node contact hole; forming a first photoresist shape, with a first opening, on said polysilicon layer; removing a portion of said first polysilicon layer, defined by said first opening, resulting in shallow trench within said polysilicon layer; plasma treating said first photoresist shape to create a second photoresist shape, with a second opening, in said second photoresist shape, with said second opening wider in diameter than said first opening, and exposing the top surface of said polysilicon layer, in regions in which said top surface of said polysilicon layer was previously protected by said first photoresist shape; ion implanting oxygen into exposed regions of said polysilicon layer; removal of said second photoresist shape; annealing to create dielectric regions, in regions of polysilicon containing oxygen ions; selective, anisotropic etching of said polysilicon layer, not covered by said dielectric regions, to create said storage node electrode, with narrow, protruding polysilicon shapes, extending upwards from a wider, flat, bottom polysilicon shape; forming a capacitor dielectric layer on said storage node electrode; and forming a polysilicon, upper electrode, for said STC structure.
Claim 13
Independent Claim
276 words
A method for fabricating a stacked capacitor structure, (STC), overlying a transfer gate transistor structure, for a DRAM device, in which a surface area of a storage node electrode is increased by formation of protruding polysilicon shapes, comprising the steps of: depositing an interlevel composite insulator layer on said transfer gate transistor; opening a storage node contact hole in said interlevel composite insulator layer, exposing a source and drain region, in a bottom of said storage node contact hole; depositing a polysilicon layer on a top surface of said interlevel composite insulator layer, and completely filling said storage node contact hole; forming a first photoresist shape, with a first opening, on said polysilicon layer; removing a portion of said first polysilicon layer, defined by said first opening, resulting in shallow trench within said polysilicon layer; plasma treating said first photoresist shape to create a second photoresist shape, with a second opening, in said second photoresist shape, with said second opening wider in diameter than said first opening, and exposing the top surface of said polysilicon layer, in regions in which said top surface of said polysilicon layer was previously protected by said first photoresist shape; ion implanting oxygen into exposed regions of said polysilicon layer; removal of said second photoresist shape; annealing to create dielectric regions, in regions of polysilicon containing oxygen ions; selective, anisotropic etching of said polysilicon layer, not covered by said dielectric regions, to create said storage node electrode, with narrow, protruding polysilicon shapes, extending upwards from a wider, flat, bottom polysilicon shape; forming a capacitor dielectric layer on said storage node electrode; and forming a polysilicon, upper electrode, for said STC structure.
Claim 14
Dependent Claim
75 words
The method of claim 11, wherein said interlevel composite insulator layer is comprised of an underlying silicon oxide layer, deposited using LPCVD or plasma enhanced chemical vapor deposition, (PECVD), procedures, at a temperature between about 400 to 700° C., to a thickness between about 1000 to 2000 Angstroms, and an overlying BPSG layer, deposited using PECVD procedures, at a temperature between about 400 to 700° C., to a thickness between about 3000 to 8000 Angstroms.
Claim 15
Dependent Claim
27 words
The method of claim 11, wherein said storage node contact hole is formed in said interlevel composite layer via RIE procedures, using CHF 3 as an etchant.
Claim 16
Dependent Claim
72 words
The method of claim 11, wherein said polysilicon layer is obtained via LPCVD procedures, at a temperature between about 500 to 700° C., to a thickness between about 3000 to 8000 Angstroms, with said polysilicon layer having an N type surface concentration between about 1E20 to 1E21 atoms/cm 3 , obtained from either LPCVD in situ doping procedures, or via ion implantation of arsenic or phosphorous, into an intrinsically grown polysilicon layer.
Claim 17
Dependent Claim
35 words
The method of claim 11, in which said shallow trench within said polysilicon layer, is created to a depth between about 1000 to 3000 Angstroms, via anisotropic RIE procedures, using Cl 2 as an etchant.
Claim 18
Dependent Claim
26 words
The method of claim 11, wherein said second opening, in said second photoresist shape, is created via an isotropic plasma treatment, using oxygen as a reactant.
Claim 19
Dependent Claim
18 words
The method of claim 11, wherein oxygen ion implantation procedure, is performed at a zero degree implantation angle.
Claim 20
Dependent Claim
30 words
The method of claim 11, wherein annealing used to create dielectric regions, in regions of said polysilicon layer containing oxygen, is performed in a nitrogen, or in an argon ambient.
Claim 21
Dependent Claim
28 words
The method of claim 11, wherein said storage node electrode is formed via selective, anisotropic RIE of said polysilicon layer, using HBr--SF 6 --Cl 2 as an etchant.
Claim 22
Dependent Claim
89 words
The method of claim 11, wherein said capacitor dielectric layer is ONO, with an equivalent silicon oxide thickness between about 40 to 80 Angstroms, created by growing a thin silicon oxide layer on said storage node electrode, at a thickness between about 10 to 50 Angstroms, depositing between about 10 to 20 Angstroms of a silicon nitride layer, and oxidizing the top portion of said silicon nitride layer to from a silicon oxynitride layer on the bottom portion of said silicon nitride layer, overlying said thin silicon oxide layer.
Claim 23
Dependent Claim
45 words
The method of claim 11, wherein said upper electrode, of said STC structure is formed from a doped polysilicon layer, deposited using LPCVD procedures to a thickness between about 1000 to 3000 Angstroms, and patterned via anisotropic RIE procedures, using Cl 2 as an etchant.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |