Process for fabricating a stacked capacitor within a monolithic integrated circuit using oxygen implantation

Claim 1

A process for fabricating a stacked capacitor from a stack of sequentially deposited layers on a wafer substrate comprising the following sequence of steps: a) deposition of a base dielectric layer on top of the substrate; b) deposition of a first polysilicon layer on top of the base dielectric layer; c) masking the first polysilicon layer with a first photoresist mask which defines a first capacitor plate; d) implanting unmasked regions of the first polysilicon layer with at least twice as many oxygen atoms per unit area as there are silicon atoms per unit area in the unmasked regions of the first polysilicon layer; e) removal of the first photoresist mask; f) thermally annealing the implanted regions of the first polysilicon layer in order to convert silicon atoms in the implanted regions into silicon dioxide; g) blanket deposition of a first capacitive dielectric layer on top of the first polysilicon layer; h) blanket deposition of a second polysilicon layer on top of the first capacitive dielectric layer; i) masking the second polysilicon layer with a second photoresist mask which defines a second capacitor plate, said second capacitor plate being horizontally misaligned with the first capacitor plate such that a first edge of the second plate overlaps a first edge of the first plate, and a second edge of the second plate underlaps a second edge of the first plate j) implanting unmasked regions of the second polysilicon layer with at least twice as many oxygen atoms per unit area as there are silicon atoms per unit area in the unmasked regions of the second polysilicon layer; k) removing the second photoresist mask; l) thermally annealing the implanted regions of the second polysilicon layer in order to convert silicon atoms in the implanted regions into silicon dioxide; m) blanket deposition of a capping dielectric layer on top of the second polysilicon layer; n) masking the capping dielectric layer with a penultimate photoresist mask that is sized and positioned such that a first edge thereof is superjacent both non-implanted regions of odd-numbered poly layers and oxygen-implanted regions of even-numbered poly layers, and a second edge thereof is superjacent both non-implanted regions of even-numbered poly layers and oxygen-implanted regions of odd-numbered poly layers; o) anisotropically etching through the layer stack, and stopping on the base dielectric layer; p) removing the penultimate photoresist mask; q) blanket deposition of a tying poly layer; r) masking the tying poly layer with a final photoresist mask so as to define a pair of non-adjacent tying layer segments, one of which is in intimate contact with non-implanted edges of odd-numbered poly layers and oxygen-implanted edges of even-numbered poly layers, the other segment being in intimate contact with non-implanted edges of even-numbered poly layers and oxygen-implanted edges of odd-numbered poly layers; and s) etching the tying poly layer so as to separate said segments.