US4700457A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making multilayer capacitor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1986-01-27
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Granted: 1987-10-20
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Expires: 2006-01-27
Abstract
Abstract A semiconductor device comprising a capacitor of a laminated structure and a method of manufacturing thereof, in which first conductive layer and second conductive layer of different materials or different compositions are stacked alternately with dielectric films interposed therebetween and the first conductive layers and the second conductive layers are interconnected respectively at a time by suitably combining a selective etching method and an anisotropic etching method.
Inventors
- 👤 Takayuki Matsukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:34
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10B; H10B12/00; H10B12/30; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
173 words
A method of manufacturing of a capacitor included in a semiconductor device formed on a semiconductor substrate, comprising the steps of: forming multiple layered film over the whole surface of said semiconductor substrate by placing alternately first conductive layer and second conductive layer of different etching characteristics with dielectric film therebetween, applying an anisotropic etching process to said multiple layered film formed by said first step so that said multiple layered film remain only in predetermined regions with all the side faces of said multiple layered film being exposed, etching all the side faces of said multiple layered film exposed by said second mentioned step using an etching process preferentially acting on said first conductive layers so that the side faces of said first conductive layers are recessed inward with the side faces of said second conductive layers being kept unchanged, filling the gaps made by said recession of said first conductive layers with an insulating material, and electrically interconnecting said second conductive layers having the exposed side faces by using a conductor.
Claim 2
Independent Claim
173 words
A method of manufacturing of a capacitor included in a semiconductor device formed on a semiconductor substrate, comprising the steps of: forming multiple layered film over the whole surface of said semiconductor substrate by placing alternately first conductive layer and second conductive layer of different etching characteristics with dielectric film therebetween, applying an anisotropic etching process to said multiple layered film formed by said first step so that said multiple layered film remain only in predetermined regions with all the side faces of said multiple layered film being exposed, etching all the side faces of said multiple layered film exposed by said second mentioned step using an etching process preferentially acting on said first conductive layers so that the side faces of said first conductive layers are recessed inward with the side faces of said second conductive layers being kept unchanged, filling the gaps made by said recession of said first conductive layers with an insulating material, and electrically interconnecting said second conductive layers having the exposed side faces by using a conductor.
Claim 3
Dependent Claim
39 words
A manufacturing method in accordance with claim 1, wherein said first conductive layers and said second conductive layers are formed on said semiconductor substrate alternately in the order of first to second layers with said dielectric film being interposed.
Claim 4
Dependent Claim
39 words
A manufacturing method in accordance with claim 1, wherein said second conductive layers and said first conductive layers are formed on said semiconductor substrate alternately in the order of second to first layers with said dielectric film being interposed.
Claim 5
Dependent Claim
78 words
A manufacturing method in accordance with claim 1, wherein said conductor used for said electrical interconnection is formed of polysilicon containing an impurity which is to be diffused in said semiconductor substrate so as to form a conductive region, said conductor being in contact with said semiconductor substrate, and said impurity is thermally diffused from said conductor into said semiconductor substrate to form an impurity diffusion region whereby said conductor is electrically connected with said impurity diffusion region.
Claim 6
Dependent Claim
78 words
A manufacturing method in accordance with claim 1, wherein said conductor used for said electrical interconnection is formed of silicide containing an impurity which is to be diffused in said semiconductor substrate so as to form a conductive region, said conductor being in contact with said semiconductor substrate, and said impurity is thermally diffused from said conductor into said semiconductor substrate to form an impurity diffusion region whereby said conductor is electrically connected with said impurity diffusion region.
Claim 7
Dependent Claim
23 words
A manufacturing method in accordance with claim 1, wherein said semiconductor device is a semiconductor memory device for storing information in said capacitor.
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