Semiconductor device with multi-layered electrodes

Claim 2

A semiconductor device comprising: (a) a first field-effect circuit element formed in a surface region of a semiconductor substrate, said first field-effect circuit element including a first gate insulating layer in a first part of the surface region of said substrate, a first gate electrode which is disposed on said first gate insulating layer and which is made of a first conductive layer, and a first interlayer insulating layer which is disposed on said first gate electrode and which has a first opening penetrating a part of said first inter-layer insulating layer; (b) a second field-effect circuit element formed in the surface region of said semiconductor substrate, said second field-effect circuit element including a second gate insulating layer in a second part of the surface region of said substrate, a second gate electrode which is made of a second conductive layer disposed so that a first part of said second gate electrode overlies said second gate insulating layer and a second part of said second gate electrode overlies said first inter-layer insulating layer at a position other than said first opening; (c) a second inter-layer insulating layer disposed on said second gate electrode and having a second penetrant opening at a predetermined position, (d) a first interconnection conductor disposed in said second opening and connected with said second gate electrode, (e) a subsidiary interconnection conductive layer disposed in said first opening, connected with said first gate electrode, and electrically isolated from said second electrode, (f) a third inter-layer insulating layer disposed on said first inter-layer insulating layer, and having a third opening, and (g) a second interconnection conductor disposed in said third opening and connected with said subsidiary interconnection conductive layer, said second interconnection conductor and said subsidiary interconnection conductive layer being formed of different conductive materials, said second interconnection conductor forming an interconnection for said first gate electrode.

Claim 3

A semiconductor device as defined in claim 1, wherein said second interconnection conductor is connected with a part of an upper surface of said subsidiary interconnection conductive layer.

Claim 4

A semiconductor device as defined in claim 2, wherein said third opening in said third inter-layer insulating layer is smaller than the upper surface area of said subsidiary interconnection conductive layer so that only a part of said upper surface area is exposed by said third opening, said exposed part of said upper surface area being that which is connected with said second interconnection conductor which is disposed in said third opening.

Claim 5

A semiconductor device as defined in claim 1 wherein said first field-effect circuit element is a capacitor in which said first gate electrode is disposed in parallel with a surface of said semiconductor substrate, which forms an inversion layer for storage of charges at a semiconductor surface portion underneath said first gate insulating layer, and wherein said second field-effect circuit element is a field-effect switching element in which said first part of said second gate electrode is disposed at a position overlying said substrate and adjoining said first gate electrode and said second part thereof is disposed on a part of said first gate electrode, and wherein said second gate insulating layer is between said first part of said second gate electrode and said semiconductor substrate surface, said field-effect switching element controlling transfer of charges into and from said capacitor.

Claim 6

A semiconductor device as defined in claim 1, further including a third field-effect circuit element in a surface region of said semiconductor substrate, said third field-effect circuit element comprising a third gate insulating layer in a layer part of the surface region of said substrate; a third gate electrode positioned on said third gate insulating layer; a lead-out electrode to be connected with a source or drain region on a fourth part of the surface region of the substrate, and a source or drain region in said semiconductor substrate.

Claim 7

A semiconductor device as defined in claim 5, further including a plurality of field isolating regions in said substrate for separating said substrate surface into a plurality of surface areas in such a manner that said first part of the surface region and said second part of the surface region are located in a first surface area and said third part of the surface region and said fourth part of the surface region are located in a second surface area, said second surface area being different from said first surface area.

Claim 8

A semiconductor device as defined in claim 5 or 6, wherein said third gate electrode, said second gate electrode and said subsidiary interconnection conductive layer are formed of the same conductive material.

Claim 9

Multi-lever electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface, at least a part of said second electrode overlying said first insulaing layer at a position other than said first opening; (c) a second insulating layer disposed on said second electrode and having a second penetrant opening at a predetermined position, (d) a first conductor disposed in said second opening and connected with said second electrode, (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode, (f) a third insulating layer disposed on said first insulating layer, and having a third opening, and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, said second conductor and said subsidiary conductive layer being formed of different materials, said second conductor forming an interconnection for said first electrode.

Claim 10

Multi-lever electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface, at least a part of said second electrode overlying said first insulaing layer at a position other than said first opening; (c) a second insulating layer disposed on said second electrode and having a second penetrant opening at a predetermined position, (d) a first conductor disposed in said second opening and connected with said second electrode, (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode, (f) a third insulating layer disposed on said first insulating layer, and having a third opening, and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, said second conductor and said subsidiary conductive layer being formed of different materials, said second conductor forming an interconnection for said first electrode.

Claim 11

Multi-level electrode structure for a semiconductor device as defined in claim 8, wherein said first electrode is a first gate electrode disposed in parallel with a surface of said semiconductor substrate, which has a first gate insulating layer disposed between said first gate electrode and said substrate surface, and which is adapted to form an inversion layer for storage of charges at a semiconductor surface portion underneath said first gate insulating layer, and wherein said second electrode is a second gate electrode, a first part thereof being disposed at a position overlying said substrate and adjoining said first gate electrode and a second part thereof being disposed on a part of said first gate electrode, and which has a second gate insulating layer between said first part of said second gate electrode and said semiconductor substrate surface.

Claim 12

Multi-level electrode structure for a semiconductor device as defined in claim 8, wherein said second conductor is connected with a part of an upper surface of said subsidiary conductive layer.

Claim 13

Multi-level electrode structure for a semiconductor device as defined in claim 10, wherein said third opening in said third insulating layer is smaller than the upper surface area of said subsidiary conductive layer so that only a part of said upper surface area is exposed by said third opening, said exposed part of said upper surface area being that which is connected with said second conductor which is disposed in said third opening.

Claim 14

A semiconductor device comprising: (a) a first field-effect circuit element formed in a surface region of a semiconductor substrate, said first field-effect circuit element including a first gate insulating layer in a first part of the surface region of said substrate, a first gate electrode which is disposed on said first gate insulating layer and which is made of a first conductive layer, and a first inter-layer insulating layer which is disposed on said first gate electrode and which has a first opening penetrating a part of said first inter-layer insulating layer; (b) a second field-effect circuit element formed in the surface region of said semiconductor substrate, said second field-effect circuit element including a second gate insulating layer in a second part of the surface region of said substrate, a second gate electrode which is made of a second conductive layer disposed so that a first part of said second gate electrode overlies said second gate insulating layer and a second part of said second gate electrode overlies said first inter-layer insulating layer at a position other than said first opening; (c) a second inter-layer insulating layer disposed on said second gate electrode and having a second penetrant opening at a predetermined position, (d) a first interconnection conductor disposed in said second opening and connected with said second gate electrode, (e) a subsidiary interconnection conductive layer disposed in said first opening, connected with said first gate electrode, and electrically isolated from said second electrode, (f) a third inter-layer insulating layer disposed on said first inter-layer insulating layer, and having a third opening, said third opening in said third inter-layer insulating layer being smaller than the upper surface area of said subsidiary interconnection conductive layer so that only a part of said upper surface area is exposed by said third opening, and (g) a second interconnection conductor disposed in said third opening and connected with said subsidiary interconnection conductive layer, the exposed part of said upper surface area of said subsidiary interconnection conductive layer being that which is connected with said second interconnection conductor, said second interconnection conductor forming an interconnection for said first gate electrode.

Claim 15

A semiconductor device comprising: (a) a first field-effect circuit element formed in a surface region of a semiconductor substrate, said first field-effect circuit element including a first gate insulating layer in a first part of the surface region of said substrate, a first gate electrode which is disposed on said first gate insulating layer and which is made of a first conductive layer, and a first inter-layer insulating layer which is disposed on said first gate electrode and which has a first opening penetrating a part of said first inter-layer insulating layer; (b) a second field-effect circuit element formed in the surface region of said semiconductor substrate, said second field-effect circuit element including a second gate insulating layer in a second part of the surface region of said substrate, a second gate electrode which is made of a second conductive layer disposed so that a first part of said second gate electrode overlies said second gate insulating layer and a second part of said second gate electrode overlies said first inter-layer insulating layer at a position other than said first opening; (c) a second inter-layer insulating layer disposed on said second gate electrode and having a second penetrant opening at a predetermined position, (d) a first interconnection conductor disposed in said second opening and connected with said second gate electrode, (e) a subsidiary interconnection conductive layer disposed in said first opening, connected with said first gate electrode, and electrically isolated from said second electrode, (f) a third inter-layer insulating layer disposed on said first inter-layer insulating layer, and having a third opening, said third opening in said third inter-layer insulating layer being smaller than the upper surface area of said subsidiary interconnection conductive layer so that only a part of said upper surface area is exposed by said third opening, and (g) a second interconnection conductor disposed in said third opening and connected with said subsidiary interconnection conductive layer, the exposed part of said upper surface area of said subsidiary interconnection conductive layer being that which is connected with said second interconnection conductor, said second interconnection conductor forming an interconnection for said first gate electrode.

Claim 16

A semiconductor device as defined in claim 12, wherein said first semiconductor circuit element is a capacitor in which said first electrode is a first gate electrode disposed in parallel with a surface of said semiconductor substrate, which has a first gate insulating layer disposed between said first gate electrode and said substrate surface, and which forms an inversion layer for storage of charges at a semiconductor surface portion underneath said first gate insulating layer, and wherein said second semiconductor circuit element is a field-effect switching element in which said second electrode is a second gate electrode, a first part thereof being disposed at a position overlying said substrate and adjoining said first gate electrode and a second part thereof being disposed on a part of said first gate electrode, and which has a second gate insulating layer between said first part of said second gate electrode and said semiconductor substrate surface, said field-effect switching element controlling transfer of charges into and from said capacitor.

Claim 17

A semiconductor device as defined in claim 12 or 13, wherein said second electrode and said subsidiary interconnection conductive layer are made of a same conductive material.

Claim 18

A semiconductor device as defined in claim 14, wherein said same conductive material is doped polycrystalline silicon.

Claim 19

A semiconductor device as defined in claim 15, wherein said first electrode is made of said same conductive material.

Claim 20

Multi-level electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface, at least a part of said second electrode overlying said first insulating layer at a position other than said first opening; (c) a second insulating layer disposed on said second electrode and having a second penetrating opening at a predetermined position, (d) a first interconnection conductor disposed in said second opening and connected with said second electrode, (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode, (f) a third insulating layer disposed on said first insulating layer, and having a third opening, said third opening being smaller than the upper surface area of said subsidiary conductive layer so that only a part of said upper surface area is exposed by said third opening, and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, the exposed part of said upper surface area of the subsidiary conductive layer being that which is connected with the second conductor which is disposed in said third opening, said second conductor forming an interconnection for said first electrode.

Claim 21

Multi-level electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface, at least a part of said second electrode overlying said first insulating layer at a position other than said first opening; (c) a second insulating layer disposed on said second electrode and having a second penetrating opening at a predetermined position, (d) a first interconnection conductor disposed in said second opening and connected with said second electrode, (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode, (f) a third insulating layer disposed on said first insulating layer, and having a third opening, said third opening being smaller than the upper surface area of said subsidiary conductive layer so that only a part of said upper surface area is exposed by said third opening, and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, the exposed part of said upper surface area of the subsidiary conductive layer being that which is connected with the second conductor which is disposed in said third opening, said second conductor forming an interconnection for said first electrode.

Claim 22

Multi-level electrode structure for a semiconductor device as defined in claim 17, wherein said first electrode is a first gate electrode disposed in parallel with a surface of said semiconductor substrate, which has a first gate insulating layer disposed between said first gate electrode and said substrate surface, and which is adpated to form an inversion layer for storage of charges at a semiconductor surface portion underneath said first gate insulating layer, and wherein said second electrode is a second gate electrode, a first part thereof being disposed at a position overlying said substrate and adjoining said first gate electrode and a second part thereof being disposed on a part of said first gate electrode, and which has a second gate insulating layer between said first part of said second gate electrode and said semiconductor substrate surface.

Claim 23

Multi-level electrode structure for a semiconductor device as defined in claim 17 or 18, wherein said second electrode and said subsidiary conductive layer are made of a same conductive material.

Claim 24

Multi-layer electrode structure for a semiconductor device as defined in claim 19, wherein said same conductive material is doped polycrystalline silicon.

Claim 25

Multi-level electrode structure for a semiconductor device as defined in claim 20, wherein said first electrode is made of said same conductive material.

Claim 26

Multi-level electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface; (c) a second insulating layer disposed on said second electrode and having a second penetrating opening at a predetermined position; (d) a first interconnection conductor disposed in said second opening and connected with said second electrode; (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode; (f) a third insulating layer disposed on said first insulating layer, and having a third opening, said third opening being smaller than the upper surface area of said subsidiary conductive layer so that only a part of said upper surface area is exposed by said third opening; and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, the exposed part of said upper surface area of the subsidiary conductive layer being that which is connected with the second conductor which is disposed in said third opening, said second conductor forming an interconnection for said first electrode.

Claim 27

Multi-level electrode structure for a semiconductor device comprising: (a) a first electrode which is disposed above a semiconductor substrate surface and which is made of a first conductive layer, and a first insulating layer which is disposed on said first electrode and which has a first opening penetrating a part of said first insulating layer; (b) a second electrode which is made of a second conductive layer disposed above said substrate surface; (c) a second insulating layer disposed on said second electrode and having a second penetrating opening at a predetermined position; (d) a first interconnection conductor disposed in said second opening and connected with said second electrode; (e) a subsidiary conductive layer disposed in said first opening, connected with said first electrode, and electrically isolated from said second electrode; (f) a third insulating layer disposed on said first insulating layer, and having a third opening, said third opening being smaller than the upper surface area of said subsidiary conductive layer so that only a part of said upper surface area is exposed by said third opening; and (g) a second conductor disposed in said third opening and connected with said subsidiary conductive layer, the exposed part of said upper surface area of the subsidiary conductive layer being that which is connected with the second conductor which is disposed in said third opening, said second conductor forming an interconnection for said first electrode.