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JPS568871A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Mitsubishi Electric Corp
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Filing: 1979-07-04
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Granted: —
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Expires: 1999-07-04
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Abstract

Abstract PURPOSE:To achieve high integration of memory devices by superimposing the parallel flat plate capacity of a memory cell on the same part of a semiconductor substrate. CONSTITUTION:A P<->-type substrate 101 is separated by P<+> layer 102 and oxide films 103 and N layers 104a, 104b are provided to connect with Al bit wires through connection windows 120a, 120b. Word wires are formed by providing N layers 105a, 105b and by making poly Si gate electrodes 107a, 107b through oxide thin films 106a, 106b. A poly Si electrode 109 is connected with the N layer 105a through a connection window 108a. Poly Si electrodes 111, 114, 117 are superinposed through insulating films and the electrode 114 is connected with the N layer 105b through a connection hole 108b. The electrode 117 is for shielding purpose. This structure effectively reduces the area per cell and permits high integration because parallel flat plate capacity is of multilayer electrode configuration.

Inventors

  • 👤 Hideyuki Ozaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-27 22:25
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30

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