Method of forming a stacked capacitor using sidewall spacers and local oxidation

Claim 1

A method for fabricating a stacked storage capacitor over a semiconductor substrate having device areas and word lines formed therein comprising the steps of: depositing a first insulating layer over said device areas, word lines and elsewhere over said substrate; forming opening in said first insulating layer to said device area and providing contact opening for a said storage capacitor node contact to said device area; depositing a first polysilicon layer over and in said contact opening and elsewhere on said substrate and making electrical node contact for said storage capacitor to said device area; depositing a second insulating layer over said first polysilicon layer; and masking and anisotropically etching an opening in said second insulating layer over and within said storage capacitor area and aligned to said node contact; depositing a third insulating layer over and in said opening and elsewhere over said second insulating layer having a different composition from said second insulating layer and forming a diffusion barrier to oxidizing atomic species; anisotropically etching back said third insulating layer to surface of said first polysilicon layer in said opening and forming sidewall spacers on said second insulating layer sidewalls; thermally and partially oxidizing said first polysilicon layer between said sidewall spacers and forming a thermal oxide layer centered in said second insulator opening; removing completely said sidewall spacers between said second insulating layer and said thermal oxide layer thereby forming an etch mask for said first polysilicon layer; anisotropically and partially etching said first polysilicon layer forming a spaced doubled recessed trench in said first polysilicon layer; removing completely said thermal oxidized layer and said second insulating layer; selectively patterning said first polysilicon layer to said first insulating layer over said device area and forming a bottom capacitor electrode depositing a dielectric layer over said bottom electrode and forming an inter-electrode insulating layer; depositing a second polysilicon layer over said dielectric layer forming a top capacitor electrode and completing said stacked storage capacitor.

Claim 2

A method for fabricating a stacked storage capacitor over a semiconductor substrate having device areas and word lines formed therein comprising the steps of: depositing a first insulating layer over said device areas, word lines and elsewhere over said substrate; forming opening in said first insulating layer to said device area and providing contact opening for a said storage capacitor node contact to said device area; depositing a first polysilicon layer over and in said contact opening and elsewhere on said substrate and making electrical node contact for said storage capacitor to said device area; depositing a second insulating layer over said first polysilicon layer; and masking and anisotropically etching an opening in said second insulating layer over and within said storage capacitor area and aligned to said node contact; depositing a third insulating layer over and in said opening and elsewhere over said second insulating layer having a different composition from said second insulating layer and forming a diffusion barrier to oxidizing atomic species; anisotropically etching back said third insulating layer to surface of said first polysilicon layer in said opening and forming sidewall spacers on said second insulating layer sidewalls; thermally and partially oxidizing said first polysilicon layer between said sidewall spacers and forming a thermal oxide layer centered in said second insulator opening; removing completely said sidewall spacers between said second insulating layer and said thermal oxide layer thereby forming an etch mask for said first polysilicon layer; anisotropically and partially etching said first polysilicon layer forming a spaced doubled recessed trench in said first polysilicon layer; removing completely said thermal oxidized layer and said second insulating layer; selectively patterning said first polysilicon layer to said first insulating layer over said device area and forming a bottom capacitor electrode depositing a dielectric layer over said bottom electrode and forming an inter-electrode insulating layer; depositing a second polysilicon layer over said dielectric layer forming a top capacitor electrode and completing said stacked storage capacitor.

Claim 13

A method for fabricating a dynamic random access memory (DRAM) cell with a metal-oxide-semiconductor field-effect-transistor (MOSFET) having device source/drains and a storage capacitors formed on and in a semiconductor substrate therein comprising the steps of forming said storage capacitor: depositing a first insulating layer over said device source/drain and elsewhere over said substrate; forming opening in said first insulating layer to said device source/drain and providing contact opening for making a storage capacitor contact to said device source/drain; depositing a first polysilicon layer over and in said contact opening and elsewhere on said substrate and making electrical node contact for said storage capacitor to said device source/drain; depositing a second insulating layer over said first polysilicon layer; and masking and anisotropically etching a ringed opening in said second insulating layer over and within said storage capacitor area and aligned to said device source/drain; depositing a third insulating layer over and in said ringed opened elsewhere over said second insulating layer having a different composition from said second insulating layer and forming a diffusion barrier to oxidizing atomic species; anisotropically etching back said third insulating layer to surface of said first polysilicon layer in said ringed opening and forming sidewall spacers on said second insulating layer sidewalls; thermally and partially oxidizing said first polysilicon layer between said sidewall spacers and forming a thermal oxide layer centered in said second insulator ringed opening; removing completely said sidewall spacers between said second insulating layer and said thermal oxide layer thereby forming an etch mask for said first polysilicon layer; anisotropically and partially etching said first polysilicon layer forming a double recessed trench in said first polysilicon layer; removing completely said thermal oxidized layer and said second insulating layer; selectively patterning said first polysilicon layer to said first insulating layer over said metal-oxide-semiconductor field-effect-transistor area and forming a bottom capacitor electrode of said storage capacitor depositing a dielectric layer over said bottom electrode and forming an inter-electrode insulating layer; depositing a second polysilicon layer over said dielectric layer forming a top capacitor electrode and making contact of said storage capacitor to said device source/drain and completing said DRAM cell.

Claim 14

A method for fabricating a dynamic random access memory (DRAM) cell with a metal-oxide-semiconductor field-effect-transistor (MOSFET) having device source/drains and a storage capacitors formed on and in a semiconductor substrate therein comprising the steps of forming said storage capacitor: depositing a first insulating layer over said device source/drain and elsewhere over said substrate; forming opening in said first insulating layer to said device source/drain and providing contact opening for making a storage capacitor contact to said device source/drain; depositing a first polysilicon layer over and in said contact opening and elsewhere on said substrate and making electrical node contact for said storage capacitor to said device source/drain; depositing a second insulating layer over said first polysilicon layer; and masking and anisotropically etching a ringed opening in said second insulating layer over and within said storage capacitor area and aligned to said device source/drain; depositing a third insulating layer over and in said ringed opened elsewhere over said second insulating layer having a different composition from said second insulating layer and forming a diffusion barrier to oxidizing atomic species; anisotropically etching back said third insulating layer to surface of said first polysilicon layer in said ringed opening and forming sidewall spacers on said second insulating layer sidewalls; thermally and partially oxidizing said first polysilicon layer between said sidewall spacers and forming a thermal oxide layer centered in said second insulator ringed opening; removing completely said sidewall spacers between said second insulating layer and said thermal oxide layer thereby forming an etch mask for said first polysilicon layer; anisotropically and partially etching said first polysilicon layer forming a double recessed trench in said first polysilicon layer; removing completely said thermal oxidized layer and said second insulating layer; selectively patterning said first polysilicon layer to said first insulating layer over said metal-oxide-semiconductor field-effect-transistor area and forming a bottom capacitor electrode of said storage capacitor depositing a dielectric layer over said bottom electrode and forming an inter-electrode insulating layer; depositing a second polysilicon layer over said dielectric layer forming a top capacitor electrode and making contact of said storage capacitor to said device source/drain and completing said DRAM cell.