Self-aligned cylindrical stacked capacitor DRAM cell

Claim 1

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer and said second polysilicon layer anisotropically with an etch mask to define the stacked capacitor areas, controlably etching said etch mask to laterally remove a certain portion of the mask and to thereby expose said second insulator layer, etching the exposed said second insulator layer and removing said etch mask, thermally oxidizing exposed said second polysilicon layer and removing the said second insulating layer, anisotropically etching said exposed second polysilicon layer through a portion of its thickness and remove said thermally oxidized layer of polysilicon, forming a capacitor dielectric layer over the said second polysilicon layer, and depositing and patterning a third polysilicon layer as the top storage node electrode to complete said stacked capacitors.

Claim 2

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer and said second polysilicon layer anisotropically with an etch mask to define the stacked capacitor areas, controlably etching said etch mask to laterally remove a certain portion of the mask and to thereby expose said second insulator layer, etching the exposed said second insulator layer and removing said etch mask, thermally oxidizing exposed said second polysilicon layer and removing the said second insulating layer, anisotropically etching said exposed second polysilicon layer through a portion of its thickness and remove said thermally oxidized layer of polysilicon, forming a capacitor dielectric layer over the said second polysilicon layer, and depositing and patterning a third polysilicon layer as the top storage node electrode to complete said stacked capacitors.

Claim 10

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer to define the stacked capacitor areas, forming sidewall spacer structure on the edges of said second insulator layer, anisotropically etch said second polysilicon layer; removing said spacer structures by etching, thermally oxidizing the exposed second polysilicon layer and then removing said second insulator layer, anisotropically etching said exposed second polysilicon layer through a portion of its thickness and remove said thermally oxidized layer of polysilicon, forming a capacitor dielectric layer over the said second polysilicon layer, and depositing and patterning a third polysilicon layer as the top storage node electrode to complete said stacked capacitors.

Claim 11

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer to define the stacked capacitor areas, forming sidewall spacer structure on the edges of said second insulator layer, anisotropically etch said second polysilicon layer; removing said spacer structures by etching, thermally oxidizing the exposed second polysilicon layer and then removing said second insulator layer, anisotropically etching said exposed second polysilicon layer through a portion of its thickness and remove said thermally oxidized layer of polysilicon, forming a capacitor dielectric layer over the said second polysilicon layer, and depositing and patterning a third polysilicon layer as the top storage node electrode to complete said stacked capacitors.

Claim 19

The method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming a source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer to define the stacked capacitor areas, forming sidewall spacer structures on the edges of said second insulator layer, anisotropically etching the exposed said second polysilicon layer, removing said second insulator layer, anisotropically etch the exposed said second polysilicon layer, forming opening to said desired source/drain structures through said first insulator using lithography techniques, removing said spacer structures by etching, depositing a contact polysilicon layer over said field oxide and device areas over the stacked capacitor areas and patterning said contact polysilicon layer to complete with said second polysilicon the lower electrode of said stacked capacitor and the contact to said source/drain structures, forming a capacitor dielectric layer over the said second polysilicon layer, depositing a contact polysilicon layer as the top storage node electrode, and patterning said dielectric layer and said third polysilicon layer to complete said stacked capacitors.

Claim 20

The method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming a source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer composed at least in part of silicon nitride over said second polysilicon layer and patterning said second insulator layer to define the stacked capacitor areas, forming sidewall spacer structures on the edges of said second insulator layer, anisotropically etching the exposed said second polysilicon layer, removing said second insulator layer, anisotropically etch the exposed said second polysilicon layer, forming opening to said desired source/drain structures through said first insulator using lithography techniques, removing said spacer structures by etching, depositing a contact polysilicon layer over said field oxide and device areas over the stacked capacitor areas and patterning said contact polysilicon layer to complete with said second polysilicon the lower electrode of said stacked capacitor and the contact to said source/drain structures, forming a capacitor dielectric layer over the said second polysilicon layer, depositing a contact polysilicon layer as the top storage node electrode, and patterning said dielectric layer and said third polysilicon layer to complete said stacked capacitors.