US5380675A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making closely spaced stacked capacitors on DRAM chips
Assignee: United Microelectronics Corp
•
Filing: 1994-03-21
•
Granted: 1995-01-10
•
Expires: 2014-03-21
Abstract
Abstract A method for fabricating an array of closely spaced storage capacitors, with increased capacitance, on a dynamic random access memory (DRAM) chip is achieved. The capacitors are increased in capacitance by minimizing the spacings between the adjacent bottom electrodes of the storage capacitors and, thereby increases the area of the capacitor electrodes. A local oxidation techniques is used to form a silicon oxide etch mask, on the bottom electrode polysilicon layer, that extends laterally under a patterned silicon nitride masking layer. This encroachment of the silicon oxide under the patterned silicon nitride layer reduces the spacing between electrodes, exceeding the resolution limits of the photoresist. The silicon nitride is removed and the silicon oxide mask is used to pattern the polysilicon layer forming an array of closely spaced polysilicon bottom electrodes. The silicon oxide is removed and an inter-electrode dielectric is deposited on the array of bottom electrode. A second doped polysilicon layer is then deposited to form the top electrode and complete the DRAM capacitors.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
313 words
A method for fabricating an array of closely spaced storage capacitors over a semiconductor substrate having an array of device regions, word lines and bit lines formed thereon comprising the steps of: depositing a first insulating layer on said substrate and electrically isolating said word lines and bit lines; depositing a second insulating layer on said first insulating layer being a different insulating material and forming a diffusion barrier; masking and anisotropically etching an array of openings in said second and first insulating layers to said device contacts in and on said array of active device regions; depositing a first polysilicon layer over said second insulating layer and over and in said array of openings making contact to said device contacts; depositing a third insulating layer over said first polysilicon layer and forming a diffusion barrier to oxidation; masking and anisotropically etching said third insulating layer to surface of said first polysilicon layer forming an array of exposed polysilicon areas over and aligned to said array of active device regions and to said device contact openings; thermally and partially oxidizing said first polysilicon layer in said array of exposed polysilicon areas and laterally under said third insulating layer; removing completely said third insulating layer between and around said array of oxidized regions exposing said first polysilicon layer; anisotropically and selectively etching said first polysilicon layer to said second insulating layer forming an array of closely spaced and completely and electrically isolated bottom capacitor electrodes formed from said first polysilicon layer; removing completely said oxidized regions over said array of bottom capacitor electrodes and forming a capacitor dielectric layer over and around said bottom capacitor electrodes; depositing a second polysilicon layer over said capacitor dielectric layer forming the top capacitor electrode and completing the array of stacked storage capacitors aligned to said array of device regions and individually and electrically contacting said device contacts.
Claim 2
Independent Claim
313 words
A method for fabricating an array of closely spaced storage capacitors over a semiconductor substrate having an array of device regions, word lines and bit lines formed thereon comprising the steps of: depositing a first insulating layer on said substrate and electrically isolating said word lines and bit lines; depositing a second insulating layer on said first insulating layer being a different insulating material and forming a diffusion barrier; masking and anisotropically etching an array of openings in said second and first insulating layers to said device contacts in and on said array of active device regions; depositing a first polysilicon layer over said second insulating layer and over and in said array of openings making contact to said device contacts; depositing a third insulating layer over said first polysilicon layer and forming a diffusion barrier to oxidation; masking and anisotropically etching said third insulating layer to surface of said first polysilicon layer forming an array of exposed polysilicon areas over and aligned to said array of active device regions and to said device contact openings; thermally and partially oxidizing said first polysilicon layer in said array of exposed polysilicon areas and laterally under said third insulating layer; removing completely said third insulating layer between and around said array of oxidized regions exposing said first polysilicon layer; anisotropically and selectively etching said first polysilicon layer to said second insulating layer forming an array of closely spaced and completely and electrically isolated bottom capacitor electrodes formed from said first polysilicon layer; removing completely said oxidized regions over said array of bottom capacitor electrodes and forming a capacitor dielectric layer over and around said bottom capacitor electrodes; depositing a second polysilicon layer over said capacitor dielectric layer forming the top capacitor electrode and completing the array of stacked storage capacitors aligned to said array of device regions and individually and electrically contacting said device contacts.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein said first insulating layer is composed of silicon oxide formed by chemical vapor deposition and having a thickness from about 1000 to 4000 Angstroms.
Claim 4
Dependent Claim
24 words
The method of claim 1, wherein said second layer is composed of silicon nitride having a thickness range from about 200 to 1000 Angstroms.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein said array of contact openings are formed comprising the steps of photo resist masking and anisotropic etching.
Claim 6
Dependent Claim
26 words
The method of claim 1, wherein said first polysilicon layer is deposited by chemical vapor deposition and having a thickness of about 2000 to 10000 Angstroms.
Claim 7
Dependent Claim
31 words
The method of claim 5, wherein said first polysilicon layer is in situ doped N-type having a concentration of between about 1 E 18 to 1 E 20 atoms/cm 3 .
Claim 8
Dependent Claim
32 words
The method of claim 5, wherein said first polysilicon layer is deposited undoped and then implanted N-type having a concentration of between 1 E 18 to 1 E 20 atoms/cm 3 .
Claim 9
Dependent Claim
27 words
The method of claim 1, wherein said array of exposed polysilicon areas are formed comprising the steps photo resist masking and anisotropic etching said third insulating layer.
Claim 10
Dependent Claim
26 words
The method of claim 1, wherein said partial thermal oxide layer in said exposed polysilicon area has a thickness of about from 2000 to 4000 Angstroms.
Claim 11
Dependent Claim
25 words
The method of claim 9, wherein said thermal oxidation is performed in an oxygen/hydrogen ambient in a temperature range of about 700° to 900° C.
Claim 12
Dependent Claim
30 words
The method of claim 1, wherein said third insulating layer is removed using a hot phosphoric acid etch having a temperature in the range from about 140° to 180° C.
Claim 13
Dependent Claim
27 words
The method of claim 1, wherein said first polysilicon layer is etched in a reactive plasma etcher having a high etch selectivity of polysilicon to silicon nitride.
Claim 14
Dependent Claim
22 words
The method of claim 1, wherein said thermal oxidized regions of said first polysilicon layer are removed by etching in hydrofluoric acid.
Claim 15
Dependent Claim
14 words
The method of claim 1, wherein said capacitor dielectric layer is silicon oxide/silicon nitride.
Claim 16
Dependent Claim
26 words
The method of claim 1, wherein said second polysilicon layer is deposited using chemical vapor deposition and having a thickness of about 2000 to 6000 Angstroms.
Claim 17
Dependent Claim
33 words
The method of claim 15, wherein said second polysilicon layer is doped in situ N-type having a concentration in the range of about 1 E 19 to 1 E 21 atoms/cm 3 .
Claim 18
Dependent Claim
31 words
The method of claim 15, wherein said second polysilicon layer is deposited undoped and then implanted having a concentration of about 1 E 19 to 1 E 21 atoms/cm 3 .
Claim 19
Dependent Claim
17 words
The method of claim 1, wherein said active device regions have metal-oxide-semiconductor field-effect transistors with source/drain regions.
Claim 20
Dependent Claim
38 words
The method of claim 18, wherein said device contacts are said source/drain regions of said metal-oxide-semiconductor field-effect-transistor forming the capacitor node contacts of the array of storage capacitors and completing the array of dynamic random access memory cells.
Claim 21
Independent Claim
313 words
A method for fabricating an array of DRAM cells with an array of Field Effect Transistor (MOSFET) having source/drains and an array of closely spaced stacked storage capacitors formed on and in a semiconductor substrate therein comprising the steps of forming said array of closely spaced storage capacitors: depositing a first insulating layer on said substrate electrically isolating word lines and bit lines; depositing a second insulating layer on said first insulating layer being a different insulating material and forming a diffusion barrier; masking and anisotropically etching an array of opening in said second and first insulating layers to said source/drains of said array of MOSFETs; depositing a first polysilicon layer over said second insulating layer and over and in said array of openings making contact to said source/drains; depositing a third insulating layer over said first polysilicon layer forming a diffusion barrier to oxidation; masking and anisotropically etching said third insulating layer to surface of said first polysilicon layer forming an array of exposed polysilicon areas over and aligned to said array of MOSFET and to said source/drains; thermally and partially oxidizing first polysilicon layer in said array of exposed polysilicon areas and laterally under said third insulating layer; removing completely said third insulating layer between and around said array of oxidized regions exposing said first polysilicon layer; anisotropically and selectively etching said first polysilicon layer to said second insulating layer forming an array of closely spaced and completely and electrically isolated bottom capacitor electrodes formed from said first polysilicon layer; removing completely said oxidized regions over said array of bottom capacitor electrodes and forming a capacitor dielectric layer over and between said bottom capacitor electrodes; depositing a second polysilicon layer over said capacitor dielectric layer forming the top capacitor electrode and completing an array of stacked storage capacitors aligned to said array of MOSFET and individually and electrically contacting said source/drains.
Claim 22
Independent Claim
313 words
A method for fabricating an array of DRAM cells with an array of Field Effect Transistor (MOSFET) having source/drains and an array of closely spaced stacked storage capacitors formed on and in a semiconductor substrate therein comprising the steps of forming said array of closely spaced storage capacitors: depositing a first insulating layer on said substrate electrically isolating word lines and bit lines; depositing a second insulating layer on said first insulating layer being a different insulating material and forming a diffusion barrier; masking and anisotropically etching an array of opening in said second and first insulating layers to said source/drains of said array of MOSFETs; depositing a first polysilicon layer over said second insulating layer and over and in said array of openings making contact to said source/drains; depositing a third insulating layer over said first polysilicon layer forming a diffusion barrier to oxidation; masking and anisotropically etching said third insulating layer to surface of said first polysilicon layer forming an array of exposed polysilicon areas over and aligned to said array of MOSFET and to said source/drains; thermally and partially oxidizing first polysilicon layer in said array of exposed polysilicon areas and laterally under said third insulating layer; removing completely said third insulating layer between and around said array of oxidized regions exposing said first polysilicon layer; anisotropically and selectively etching said first polysilicon layer to said second insulating layer forming an array of closely spaced and completely and electrically isolated bottom capacitor electrodes formed from said first polysilicon layer; removing completely said oxidized regions over said array of bottom capacitor electrodes and forming a capacitor dielectric layer over and between said bottom capacitor electrodes; depositing a second polysilicon layer over said capacitor dielectric layer forming the top capacitor electrode and completing an array of stacked storage capacitors aligned to said array of MOSFET and individually and electrically contacting said source/drains.
Claim 23
Dependent Claim
30 words
The method of claim 20, wherein said first insulating layer is composed of silicon oxide formed by chemical vapor deposition and having a thickness from about 1000 to 4000 Angstroms.
Claim 24
Dependent Claim
26 words
The method of claim 20, wherein said second layer is composed of silicon nitride having a thickness in the range from about 200 to 1000 Angstroms.
Claim 25
Dependent Claim
23 words
The method of claim 20, wherein said array of contact openings are formed comprising the steps of photo resist masking and anisotropic etching.
Claim 26
Dependent Claim
26 words
The method of claim 20, wherein said first polysilicon layer is deposited by chemical vapor deposition and having a thickness of about 2000 to 10000 Angstroms.
Claim 27
Dependent Claim
31 words
The method of claim 24, wherein said first polysilicon layer is in situ doped N-type having a concentration from between about 1 E 18 to 1 E 20 atoms/cm 3 .
Claim 28
Dependent Claim
33 words
The method of claim 24, wherein said first polysilicon layer is deposited undoped and then implanted N-type having a concentration from between about 1 E 18 to 1 E 20 atoms/cm 3 .
Claim 29
Dependent Claim
27 words
The method of claim 20, wherein said array of exposed polysilicon areas are formed comprising the steps photo resist masking and anisotropic etching said third insulating layer.
Claim 30
Dependent Claim
26 words
The method of claim 20, wherein said partial thermal oxide layer in said exposed polysilicon area has a thickness of about from 2000 to 4000 Angstroms.
Claim 31
Dependent Claim
25 words
The method of claim 28, wherein said thermal oxidation is performed in an oxygen/hydrogen ambient having a temperature range of about 700° to 900° C.
Claim 32
Dependent Claim
29 words
The method of claim 20, wherein said third insulating layer is removed by hot phosphoric acid etching having a temperature in the range from about 140° to 180° C.
Claim 33
Dependent Claim
27 words
The method of claim 20, wherein said first polysilicon layer is etched in a reactive plasma etcher having a high etch selectivity of polysilicon to silicon nitride.
Claim 34
Dependent Claim
15 words
The method of claim 20, wherein said oxidized regions are removed by hydrofluoric acid etching.
Claim 35
Dependent Claim
14 words
The method of claim 20, wherein said capacitor dielectric layer is silicon oxide/silicon nitride.
Claim 36
Dependent Claim
26 words
The method of claim 20, wherein said second polysilicon layer is deposited using chemical vapor deposition and having a thickness of about 2000 to 6000 Angstroms.
Claim 37
Dependent Claim
33 words
The method of claim 34, wherein said second polysilicon layer is doped in situ N-type having a concentration in the range of about 1 E 19 to 1 E 21 atoms/cm 3 .
Claim 38
Dependent Claim
31 words
The method of claim 35, wherein said second polysilicon layer is deposited undoped and then implanted having a concentration of about 1 E 19 to 1 E 21 atoms/cm 3 .
Claim 39
Dependent Claim
30 words
The method of claim 20, wherein said array of storage capacitor are formed over and aligned to said array of metal-oxide-semiconductor field-effect transistors and making electrical contact to said source/drains
Claim 40
Dependent Claim
28 words
The method of claim 20, wherein said array of storage capacitors contact said array of metal-oxide-semiconductor field-effect transistor source/drains completing said array of dynamic random access memory cells.
References Cited (Backward Citations)
US4977102A
Cited
US5162881A
Cited
US5066604A
Cited
US5061650A
Cited
US5262343A
Cited
US5192702A
Cited
US5266514A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |