US5804481A
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US
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Increased capacitor surface area via use of an oxide formation and removal procedure
Assignee: Vanguard International Semiconductor Corp
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Filing: 1997-03-10
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Granted: 1998-09-08
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Expires: 2017-03-10
Abstract
Abstract A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. Thermal oxidation creates thick silicon oxide regions in areas of exposed doped polysilicon, while thinner silicon oxide regions form in areas in which the intrinsic HSG polysilicon spots are oxidized. Removal of both thick and thinner silicon oxide regions, creates the saw-toothed topography in the polysilicon storage node electrode, resulting in surface area, and capacitance increases.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033; Y; Y10; Y10S; Y10S438/00; Y10S438/964
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
357 words
A method of fabricating a DRAM device, on a semiconductor substrate, comprised of an underlying transistor; with a gate insulator, a gate electrode structure, formed from a first insulator layer, and from a first polysilicon layer, insulator sidewall spacers, formed from a second insulator layer, and source and drain regions, and an overlying STC structure; with a polysilicon storage node electrode, a dielectric layer, and an overlying polysilicon plate electrode, and with the top surface of said polysilicon storage node electrode, exhibiting a saw-toothed topography, comprising the steps of: depositing a third insulator layer, on said underlying transistor of said DRAM device; depositing a doped dielectric layer on said third insulator layer; planarizing said doped dielectric layer; opening a contact hole, in said doped dielectric layer, and in said third insulator layer, to expose top surface of said source and drain regions, of said underlying transistor; depositing a doped, second polysilicon layer on top surface of said doped dielectric layer, and on top surface of said source and drain regions, exposed in said contact hole; depositing intrinsic HSG polysilicon spots on said doped second polysilicon layer; oxidizing said intrinsic HSG polysilicon spots to form a first silicon oxide region, on the top surface of said doped second polysilicon layer; oxidizing a top portion of said doped second polysilicon layer, exposed between said intrinsic HSG polysilicon spots, to form a second silicon oxide region, thicker then said first silicon oxide region, overlying lower portions of said doped second polysilicon layer; removing said first silicon oxide region, exposing top surface of raised portions of said doped second polysilicon layer, and removing said second silicon oxide region, exposing top surface of said lower portions of said doped second polysilicon layer, resulting in a saw-toothed topography, comprised of raised and lower features in said doped second polysilicon layer; patterning of said doped second polysilicon layer, to create said polysilicon storage node electrode, with said saw-toothed topography; forming said dielectric layer on said polysilicon storage node electrode; depositing a third polysilicon layer on said dielectric layer; and patterning of said third polysilicon layer to form said plate electrode, of said STC structure.
Claim 2
Independent Claim
357 words
A method of fabricating a DRAM device, on a semiconductor substrate, comprised of an underlying transistor; with a gate insulator, a gate electrode structure, formed from a first insulator layer, and from a first polysilicon layer, insulator sidewall spacers, formed from a second insulator layer, and source and drain regions, and an overlying STC structure; with a polysilicon storage node electrode, a dielectric layer, and an overlying polysilicon plate electrode, and with the top surface of said polysilicon storage node electrode, exhibiting a saw-toothed topography, comprising the steps of: depositing a third insulator layer, on said underlying transistor of said DRAM device; depositing a doped dielectric layer on said third insulator layer; planarizing said doped dielectric layer; opening a contact hole, in said doped dielectric layer, and in said third insulator layer, to expose top surface of said source and drain regions, of said underlying transistor; depositing a doped, second polysilicon layer on top surface of said doped dielectric layer, and on top surface of said source and drain regions, exposed in said contact hole; depositing intrinsic HSG polysilicon spots on said doped second polysilicon layer; oxidizing said intrinsic HSG polysilicon spots to form a first silicon oxide region, on the top surface of said doped second polysilicon layer; oxidizing a top portion of said doped second polysilicon layer, exposed between said intrinsic HSG polysilicon spots, to form a second silicon oxide region, thicker then said first silicon oxide region, overlying lower portions of said doped second polysilicon layer; removing said first silicon oxide region, exposing top surface of raised portions of said doped second polysilicon layer, and removing said second silicon oxide region, exposing top surface of said lower portions of said doped second polysilicon layer, resulting in a saw-toothed topography, comprised of raised and lower features in said doped second polysilicon layer; patterning of said doped second polysilicon layer, to create said polysilicon storage node electrode, with said saw-toothed topography; forming said dielectric layer on said polysilicon storage node electrode; depositing a third polysilicon layer on said dielectric layer; and patterning of said third polysilicon layer to form said plate electrode, of said STC structure.
Claim 3
Dependent Claim
65 words
The method of claim 1, wherein said doped second polysilicon layer is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 4000 Angstroms, with a N type dopant concentration between about 1E20 to 1E21 atoms/cm 3 , obtained using in situ doping procedures, via the addition of phosphine or arsine to a silane ambient.
Claim 4
Dependent Claim
40 words
The method of claim 1, wherein said intrinsic HSG polysilicon spots are deposited at a temperature between about 500° to 700° C., to a thickness between about 100 to 1000 Angstroms, with a diameter between about 50 to 500 Angstroms.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein the space between said intrinsic HSG polysilicon spots is between about 100 to 1000 Angstroms.
Claim 6
Dependent Claim
44 words
The method of claim 1, wherein said first silicon oxide region is grown via thermal oxidation of said intrinsic HSG polysilicon spots, in an oxygen--steam ambient, at a temperature between about 700° to 900° C., to a thickness between about 200 to 1000 Angstroms.
Claim 7
Dependent Claim
44 words
The method of claim 1, wherein said second silicon oxide region is grown via thermal oxidation of said doped second polysilicon layer, in an oxygen--steam ambient, at a temperature between about 700° to 900° C., to a thickness between about 300 to 2000 Angstroms.
Claim 8
Dependent Claim
30 words
The method of claim 1, wherein said first silicon oxide region, and said second silicon oxide region, are removed via use of wet etching using a dilute hydrofluoric acid solution.
Claim 9
Dependent Claim
54 words
The method of claim 1, wherein said saw-toothed topography, of said doped second polysilicon layer, is comprised of raised portions, and lower portions of said doped second polysilicon layer, with the difference in height between said raised portions, and said lower portions, of said doped second polysilicon layer, between about 400 to 2000 Angstroms.
Claim 10
Dependent Claim
77 words
The method of claim 1, wherein said dielectric layer is ONO, at an equivalent silicon dioxide thickness between about 40 to 80 Angstroms, created by an initial thermal oxidation to form a silicon oxide layer, between about 10 to 50 Angstroms, followed by a deposition of silicon nitride, to a thickness between about 10 to 20 Angstroms, and thermal oxidation of said silicon nitride layer, creating a silicon oxynitride layer, on the underlying, said silicon oxide layer.
Claim 11
Dependent Claim
44 words
The method of claim 1, wherein said third polysilicon layer, used for creation of said polysilicon plate electrode of said STC structure, is deposited using LPCVD procedures, at a temperature between about 500° to 700°C., to a thickness between about 1000 to 2000 Angstroms.
Claim 12
Independent Claim
353 words
A method of fabricating a stacked capacitor structure, (STC), for a DRAM device, in which the surface area of the polysilicon storage node electrode is increased via use of a polysilicon storage node electrode, exhibiting a saw-tooth topography, obtained via oxidation of doped and intrinsic polysilicon regions, comprising the steps of: depositing a first insulator layer on an underlying transistor structure, of said DRAM device; depositing a doped dielectric layer on said first insulator layer; planarizing said doped dielectric layer; opening a contact hole in said doped dielectric layer, and in said first insulator layer, to expose top surface of said underlying transistor region; depositing a doped, first polysilicon layer on top surface of said doped dielectric layer, and on said top surface of said underlying transistor region, exposed in said contact hole; depositing intrinsic HSG polysilicon spots on said doped, first polysilicon layer; oxidizing said intrinsic HSG polysilicon spots, to form a thin silicon oxide region on the top surface of a first region of said doped, first polysilicon layer; oxidizing a top portion, of a second region of said doped, first polysilicon layer, exposed between said intrinsic HSG polysilicon spots, to form a thick silicon oxide region, on the top surface, of a bottom portion of a second region of said doped, first polysilicon layer; removing said thin silicon oxide region, exposing the top surface of said first region of said doped, first polysilicon layer, and removing said thick silicon oxide region, exposing the top surface, of a bottom portion of said doped, first polysilicon layer, in said second region, resulting in a saw-toothed topography, comprised of raised doped, first polysilicon features in said first region of said doped, first polysilicon layer, and lower doped, first polysilicon features in said second region of said doped, first polysilicon layer; patterning of said doped, first polysilicon layer to create said polysilicon storage node electrode, with said saw-toothed topography; forming a dielectric layer on saw-toothed polysilicon storage node electrode; depositing a second polysilicon layer on said dielectric layer; and patterning of said second polysilicon layer to form polysilicon plate electrode, of said STC structure.
Claim 13
Independent Claim
353 words
A method of fabricating a stacked capacitor structure, (STC), for a DRAM device, in which the surface area of the polysilicon storage node electrode is increased via use of a polysilicon storage node electrode, exhibiting a saw-tooth topography, obtained via oxidation of doped and intrinsic polysilicon regions, comprising the steps of: depositing a first insulator layer on an underlying transistor structure, of said DRAM device; depositing a doped dielectric layer on said first insulator layer; planarizing said doped dielectric layer; opening a contact hole in said doped dielectric layer, and in said first insulator layer, to expose top surface of said underlying transistor region; depositing a doped, first polysilicon layer on top surface of said doped dielectric layer, and on said top surface of said underlying transistor region, exposed in said contact hole; depositing intrinsic HSG polysilicon spots on said doped, first polysilicon layer; oxidizing said intrinsic HSG polysilicon spots, to form a thin silicon oxide region on the top surface of a first region of said doped, first polysilicon layer; oxidizing a top portion, of a second region of said doped, first polysilicon layer, exposed between said intrinsic HSG polysilicon spots, to form a thick silicon oxide region, on the top surface, of a bottom portion of a second region of said doped, first polysilicon layer; removing said thin silicon oxide region, exposing the top surface of said first region of said doped, first polysilicon layer, and removing said thick silicon oxide region, exposing the top surface, of a bottom portion of said doped, first polysilicon layer, in said second region, resulting in a saw-toothed topography, comprised of raised doped, first polysilicon features in said first region of said doped, first polysilicon layer, and lower doped, first polysilicon features in said second region of said doped, first polysilicon layer; patterning of said doped, first polysilicon layer to create said polysilicon storage node electrode, with said saw-toothed topography; forming a dielectric layer on saw-toothed polysilicon storage node electrode; depositing a second polysilicon layer on said dielectric layer; and patterning of said second polysilicon layer to form polysilicon plate electrode, of said STC structure.
Claim 14
Dependent Claim
67 words
The method of claim 11, wherein said doped, first polysilicon layer is obtained via LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 4000 Angstroms, with an N type dopant concentration between about 1E20 to 1E21 atoms/cm 3 , obtained using an in situ doping procedure via the addition of either phosphine or arsine to a silane ambient.
Claim 15
Dependent Claim
40 words
The method of claim 11, wherein said intrinsic HSG polysilicon spots are deposited at a temperature between about 500° to 700° C., to a thickness between about 100 to 1000 Angstroms, with a diameter between about 50 to 500 Angstroms.
Claim 16
Dependent Claim
21 words
The method of claim 11, wherein the space between said intrinsic HSG polysilicon spots is between about 100 to 1000 Angstroms.
Claim 17
Dependent Claim
59 words
The method of claim 11, wherein said thin silicon oxide region, located on the top surface, of a first region of said doped, first polysilicon layer, is grown via thermal oxidation of said intrinsic HSG polysilicon spots, in an oxygen--steam ambient, at a temperature between about 700° to 900° C., to a thickness between about 200 to 1000 Angstroms.
Claim 18
Dependent Claim
67 words
The method of claim 11, wherein said thick silicon oxide region, located on the top surface, of a bottom portion of a second region of said doped, first polysilicon layer, is grown via thermal oxidation of said second region, of said doped, first polysilicon layer, in an oxygen--steam ambient, at a temperature between about 700° to 900° C., to a thickness between about 300 to 2000 Angstroms.
Claim 19
Dependent Claim
26 words
The method of claim 11, wherein said thin silicon region, and said thick silicon oxide region, are removed via use of a dilute hydrofluoric acid solution.
Claim 20
Dependent Claim
70 words
The method of claim 11, wherein said saw-toothed topography of said doped, first polysilicon layer is comprised of raised, doped, first polysilicon features, in a first region of said doped, first polysilicon layer, and lower, doped, first polysilicon features, in a second region of said doped, first polysilicon layer, with the difference in height between said raised polysilicon features, and said lower polysilicon features, between about 400 to 2000 Angstroms.
Claim 21
Dependent Claim
75 words
The method of claim 11, wherein said dielectric layer is ONO, with an equivalent silicon oxide thickness between about 40 to 80 Angstroms, created by growing a thin silicon oxide layer on said storage node electrode, at a thickness between about 10 to 50 Angstroms, depositing between about 10 to 20 Angstroms of a silicon nitride layer, and oxidizing said silicon nitride layer to from a silicon oxynitride layer on said thin silicon oxide layer.
Claim 22
Dependent Claim
33 words
The method of claim 11, wherein said second polysilicon layer is deposited using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 2000 Angstroms.
Claim 23
Dependent Claim
25 words
The method of claim 11, wherein said polysilicon plate electrode is created via RIE of said second polysilicon layer, using Cl 2 as an etchant.
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