US5492848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked capacitor process using silicon nodules
Assignee: United Microelectronics Corp
•
Filing: 1994-03-18
•
Granted: 1996-02-20
•
Expires: 2014-03-18
Abstract
Abstract A technique for making a MOST capacitor for use in a DRAM cell utilizes silicon nodules after metal etching. The silicon nodules are used as a mask to selectively form deep grooves in a polysilicon electrode of the capacitor.
Inventors
- 👤 Water Lur
- 👤 Jiunn-Yuan Wu
- 👤 Cheng-Hen Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:20
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
129 words
A method for making a MOST capacitor for use in a DRAM cell comprising the steps of (a) forming a conductive polysilicon layer on a silicon substrate, (b) forming an oxide layer on the polysilicon layer, (c) forming a metal layer on the oxide layer, (d) forming silicon precipitates in the metal layer, (e) reactive ion etching said metal layer to form silicon nodules on the oxide layer, (f) using the silicon nodules as a mask, reactive ion etching the oxide layer to form a plurality of oxide islands, (g) using the oxide islands as a mask, etching the polysilicon layer to form a plurality of pillars, (h) forming a capacitor dielectric layer on the etched polysilicon layer, and (i) forming a second polysilicon layer on the dielectric layer.
Claim 2
Independent Claim
129 words
A method for making a MOST capacitor for use in a DRAM cell comprising the steps of (a) forming a conductive polysilicon layer on a silicon substrate, (b) forming an oxide layer on the polysilicon layer, (c) forming a metal layer on the oxide layer, (d) forming silicon precipitates in the metal layer, (e) reactive ion etching said metal layer to form silicon nodules on the oxide layer, (f) using the silicon nodules as a mask, reactive ion etching the oxide layer to form a plurality of oxide islands, (g) using the oxide islands as a mask, etching the polysilicon layer to form a plurality of pillars, (h) forming a capacitor dielectric layer on the etched polysilicon layer, and (i) forming a second polysilicon layer on the dielectric layer.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein said nodules have a size in the range of 0.05-0.2 microns.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said step of forming the metal layer forms an aluminum-silicon alloy layer on the oxide layer.
Claim 5
Dependent Claim
31 words
The method of claim 3 further comprising the step of, after said step of forming said aluminum-silicon alloy layer, heating said aluminum-silicon alloy layer to a temperature of approximately 400° C.
References Cited (Backward Citations)
US4859622A
Cited
JPH02308551A
Cited
JPH03266460A
Cited
US5304828A
Cited
US5332696A
Cited
US5158905A
Cited
US5164881A
Cited
US5134086A
Cited
US5256587A
Cited
US5182232A
Cited
US5313100A
Cited
US5068199A
Cited
US5110752A
Cited
US5227322A
Cited
US5213992A
Cited
US5342800A
Cited
US5302540A
Cited
US5350707A
Cited
US5244842A
Cited
US5358888A
Cited
US5204280A
Cited
US5254503A
Cited
US5308786A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |