Fabrication method for capacitor of stack-type DRAM cell

Claim 1

A fabrication method for a capacitor of a stacked DRAM cell comprising: forming a first insulating film, an anti-etching film, and a first conductive film on a substrate by which a switching transistor and a bit line formed previously are buried; forming a patterned second insulating film on a first conductive film in such a manner that patterned portions of the second insulating film are formed having a predetermined spacing therebetween; forming a second conductive film on the first conductive film and the patterned second insulating film thereon; dry-etching the first and second conductive films to expose a portion of the surface of the anti-etching film therethrough; forming a contact hole by etching the exposed surface of the anti-etching film and the first insulating film therebeneath; forming a third conductive film over the surfaces of the first and the second conductive films, including the contact hole therebetween; forming a planarized fourth insulating film over the third conductive film; etching the fourth insulating film to expose portion of the surface of the anti-etching film above the bit line and then etching the third and the first conductive films; forming sidewalls composed of a fourth conductive film at sides of the fourth insulating film, the third and first conductive films and forming a node electrode composed of the first through fourth conductive films; stripping the fourth insulating film, forming a dielectric film over the surfaces of the node electrode and the anti-etching film; and forming a plate electrode over the dielectric film.